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| never stop thinking. hyb18t256161af?22/25/28/33 HYB18T256161AFL25/28/33 256-mbit x16 gddr2 dram rohs compliant data sheet, rev. 1.30, july 2005 memory products
edition 2005-07 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet 3 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram hyb18t256161af?22/25/28/33 HYB18T256161AFL25/28/33 revision history: rev. 1.30 2005-07 previous revision: rev. 1.2 page subjects (major changes since last revision) all added speed sort l25, l28, l33 we listen to your comments any information within this do cument that you feel is wro ng, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com hyb18t256161af?[22/25/28/ 33] l[25/28/33] 256-mbit ddr2 sgram data sheet 4 rev. 1.30, 2005-07 11222004-7n66-547b 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 256mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6 input/output functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.7 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 programming the mode register and extended mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3 ddr2 sdram mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.4 ddr2 sdram extended mode register set (emrs(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 emrs(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.6 emrs(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 off-chip driver (ocd) impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 extended mode register set for ocd impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.5 bank activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 read and write commands and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6.1 posted cas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6.2 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.3 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6.4 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.5 write data mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.6 burst interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.7 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.7.1 read operation followed by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.7.2 write followed by precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.8 auto-precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.8.1 read with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.8.2 write with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.8.3 read or write to precharge command spacing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.8.4 concurrent auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.9 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9.1 auto-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9.2 self-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.10 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.11 other commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.11.1 no operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.11.2 deselect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.12 dll-off mode clock speed operation range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.13 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.14 asynchronous cke low reset event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table of content hyb18t256161af?[22/25/28/ 33] l[25/28/33] 256-mbit ddr2 sgram data sheet 5 rev. 1.30, 2005-07 11222004-7n66-547b 5.3 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.4 default output v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4.1 calibrated output driver v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6 power & ground clamp v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.7 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 on die termination (odt) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7 electrical characteristics & ac timing - absolute specification . . . . . . . . . . . . . . . . . . . . . . . . 75 8 ac timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.1 reference load for timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2 slew rate measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2.1 output slewrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2.2 input slewrate - differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2.3 input slewrate - single ended signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3 input and data setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.3.1 timing definition for input setup ( t is ) and hold time ( t ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes . . . . . . . . . . . . . . . . 82 8.3.3 definition for data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes . . . . . . . . . . . . . 83 8.3.4 slew rate definition for input and data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.1 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.2 package thermal characterist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview data sheet 6 rev. 1.30, 2005-07 11222004-7n66-547b 1overview this chapter gives an overview of the 256-mbit x1 6 gddr2 dram product family and describes its main characteristics. 1.1 features the 256-mbit x16 gddr2 dram is optim ized for graphics applications and offers the followi ng key features: ? 2.0v +/- 0.1v vdd core voltage (hyb18t256161af-22/-25/-28/-33) ? 2.0v +/- 0.1v vddq io voltage (hyb18t256161af-22/-25/-28/-33) ? 1.8v +/- 0.1v vdd core voltage (HYB18T256161AFL25/28/33) ? 1.8v +/- 0.1v vddq io voltage (HYB18T256161AFL25/28/33) ? dll-off mode operation support ? dram organisations with 16 data in/outputs ? double data rate architec ture: two data transfers per clock cycle, internal banks for concurrent operation ? cas latency: 5 and 6 ? burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differential data strobes (dqs and dqs ) are transmitted / rece ived with data. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-ref resh and power saving power-down modes ? normal and weak streng th data-output drivers ? 1k page size ? packages: pg-tfbga 84 1.2 ordering information 1.3 description the 256-mbit x16 gddr2 dramis a high-speed double-data-rate-2 cmos synchronous dram device containing 268,435,456 bits and internally configured as a q-bank dram. the 256-mbit x16 gddr2 dramis organized as hip. these synchronous devices achieve high speed transfer rates up to 900 mb/sec/pin and is optimized for graphics performance. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. off-chip driver (ocd) impedance adjustment and 5. an on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 1is used to convey row, column and bank address information in a ras-cas multiplexing style. the desktop ddr2 device opera tes at a 2.0v +/- 0.1v, the low power device at 1.8v +/- 0.1v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. table 1 ordering information part number org. package hyb18t256161af-22/-25/-28/-33 16mx16 pg-tfbga 84 HYB18T256161AFL25/l28/l33 data sheet 7 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the 256-mbit x16 gddr2 dram is available in p-tfbga package. 1.4 pin configuration the pin configuration of a 256-mbit x16 gddr2 dram is listed by function in table 2 . the abbreviations used in the pin#/buffer type columns are explained in table 3 and table 4 respectively. the pin numbering for the fbga package is depicted in figure 1 . table 2 pin configuration of 256-mbit x16 gddr2 dram ball#/pin# name pin type buffer type function clock signals organization j8 ck i sstl clock signal k8 ck i sstl complementary clock signal k2 cke i sstl clock enable rank control signals organization k7 ras i sstl row address strobe l7 cas i sstl column address strobe k3 we i sstl write enable l8 cs i sstl chip select l8 a13 i sstl address signal 13 address signals organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ? m8 a0 i sstl address signal 12:0 m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals organization g8 dq0 i/o sstl data signal 0 g2 dq1 i/o sstl data signal 1 h7 dq2 i/o sstl data signal 2 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview data sheet 8 rev. 1.30, 2005-07 11222004-7n66-547b h3 dq3 i/o sstl data signal 3 h1 dq4 i/o sstl data signal 4 h9 dq5 i/o sstl data signal 5 f1 dq6 i/o sstl data signal 6 f9 dq7 i/o sstl data signal 7 c8 dq8 i/o sstl data signal 8 c2 dq9 i/o sstl data signal 9 d7 dq10 i/o sstl data signal 10 d3 dq11 i/o sstl data signal 11 d1 dq12 i/o sstl data signal 12 d9 dq13 i/o sstl data signal 13 b1 dq14 i/o sstl data signal 14 b9 dq15 i/o sstl data signal 15 data strobe organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl data strobe upper byte f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data strobe lower byte data mask organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte power supplies organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins organization k9 odt ? ? on-die termination control table 2 pin configuration of 256-mbit x16 gddr2 dram ball#/pin# name pin type buffer type function data sheet 9 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview table 3 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 4 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview data sheet 10 rev. 1.30, 2005-07 11222004-7n66-547b figure 1 pin configuration pg-tfbga 84 top view, see the balls throught the package notes 1. udqs/udqs is data strobe for upper byte, ldqs/ldqs is data strobe for lower byte 2. udm is the data mask signal for the upper byte udq[7:0], ldm is the data ma sk signal for the lower byte dq[7:0] 3. v ddl and v ddsl are power and ground respectively for the dll. v ddl connected to v dd , and v ddsl connected to v ss . mppt0110 cs ba0 dq14 a10/ap a3 a7 a12 a1 a5 a9 nc v ss 123 a2 a6 a4 udq2 udqs 7 v ssdl v ssq v ddq v ssq a0 nc a11 8 v ddq dq15 dq8 dq13 9 a b c d f g h j e l k v dd v ssq v ddq dq9 v ddq we ck ba1 nc/ba2 v ss v dd cas udqs v ddq v ssq ck v dd ras odt v dd a8 v ss nc/a13 m n r p nc udm nc v ss dq6 v ssq ldm v ddq dq1 v ddq dq12 v ssq dq11 dq4 v ssq dq3 v ddl v ref v ss cke v ssq ldqs v ddq ldqs v ssq dq7 v ddq dq0 v ddq dq2 v ssq dq5 v dd 456 data sheet 11 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview 1.5 256mbit ddr2 addressing 1.6 input/output functional description table 5 256 mbit ddr2 addressing configuration 16 x 16 note number of banks 4 bank address ba[0:1]] auto-precharge a10 / ap row address a[12:0] column address a[8:0] number of column address bits 9 number of i/os 16 page size [bytes] 1024 (1k) table 6 input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. a ll address and control inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both directions of crossing). cke input clock enable: cke high activates and cke low deactivates internal clock signals and device input buffers and output driver s. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous fo r power down entry and exit and for self- refresh entry. input buffers excluding cke are disabled during self-refresh. cke is used asynchronously to detect self-refresh exit condition. self-r efresh termination itself is synchronous. after vref has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck, odt and cke are disabled during power-down. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on sys tems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the emrs(1) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered dm, ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ldm and udm are the input mask signals and control the lower or upper bytes. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview data sheet 12 rev. 1.30, 2005-07 11222004-7n66-547b ba[1:0] input bank address inputs: define to which bank an activate, read, write or precharge command is being applied. ba[1:0] also determ ines if the mode register or extended mode register is to be accessed during a mrs or emrs(1) cycle. a[12:0] input address inputs: provides the row address for activate commands and the column address and auto-precharge bit a10 (=ap) for read/write comm ands to select one location out of the memory array in the re spective bank. a10 (=ap) is sampled during a precharge command to determine whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be precharged, the bank is selected by ba[1:0]. the address inputs also provide the op-code during mode register set commands. dq[0:15] input/ output data inputs/output: bi-directional data bus. dqs, (dqs ) ldqs, (ldqs ), udqs,(udqs ) input/ output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. ldqs corresponds to the data on dq[7:0]; udqs corresponds to the data on dq[15:8]. t he data strobes dqs, ldqs, udqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals. nc ? no connect: no internal electrical connection is present v ddq supply dq power supply: 2.0v +/- 0.1v for desktop 1.8v +/- 0.1v for low power v ssq supply dq ground v ddl supply dll power supply: (internally connected to v dd ) 2.0v +/- 0.1v for desktop 1.8v +/- 0.1v for low power v ssdl supply dll ground (internally connected to v ss ) v dd supply power supply: 2.0v +/- 0.1v for desktop 1.8v +/- 0.1v for low power v ss supply ground v ref supply reference voltage table 6 input/output functional description symbol type function data sheet 13 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram overview 1.7 block diagrams figure 2 block diagram 4 mbit 16 i/o 4 internal memory banks note: 1. 16 mb 16 organisation with 13 row, 2 bank and 10 column external adresses. 2. this functional block diagram is intended to facilitate user understandin g of the operation of the device; it does not represent an actual circuit implementation. 3. ldm, udm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional ldqs and udqs signals. - 0 " 4 # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o n t r o l , o g i c 2 o w ! d d r e s s - 5 8 ) / ' a t i n g $ - - a s k , o g i c 2 e f r e s h # o u n t e r # o l u m n ! d d r e s s # o u n t e r , a t c h # / , ! d d r e s s 2 e g i s t e r - o d e 2 e g i s t e r s # o m m a n d $ e c o d e 2 ! 3 # ! 3 7 % # 3 # + # + # + % ! ! " ! " ! $ a t a - a s k 7 r i t e & ) & / $ r i v e r s # / , # + # + 2 e c e i v e r s ) n p u t 2 e g i s t e r - 5 8 # / , $ 1 3 ' e n e r a t o r $ r i v e r s $ a t a $ 1 3 $ 1 3 2 e a d , a t c h $ , , # + # + 5 $ 1 3 5 $ 1 3 $ 1 $ 1 / $ 4 # o n t r o l 5 $ - , $ - , $ 1 3 , $ 1 3 / $ 4 " a n k " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k " a n k x " a n k " a n k " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r " a n k " a n k # o n t r o l , o g i c hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 14 rev. 1.30, 2005-07 11222004-7n66-547b 2 functional description 2.1 simplified state diagram figure 3 simplified state diagram note: this simplified state diagram is intended to provide a floorplan of the possible state transitions and thecommands to control them. in particular situations involving more than one bank, enabling / disabling on-die termination, power-down entry / exit - among other things - are not captured in full detail. - 0 & 4 " a n k ! c t i v e 2 e a d i n g ? ! 0 2 e a d i n g 7 r i t i n g ? ! 0 7 r i t i n g ! c t i v a t i n g ) d l e 2 , " , t 2 4 0 3 e t t i n g - 2 3 o r % - 2 3 3 e l f 2 e f r e s h 2 % & 3 0 r e c h a r g e 0 $ ) n i t i a l i z a t i o n 3 e q u e n c e ! u t o m a t i c 3 e q u e n c e # o m m a n d 3 e q u e n c e ! c t i v e 0 $ # + % , 0 $ ? e n t r y # + % ( 7 r i t e 7 r i t e 2 e a d 2 e a d 0 r e c h a r g i n g 0 2 % 2 e a d ? ! 0 7 r i t e ? ! 0 t 2 0 0 2 % t 2 # $ 7 , " , 7 2 ! # 4 t - 2 $ - 2 3 0 $ ? e n t r y # + % ( # + % , # + % , ! u t o 2 e f r e s h i n g t 2 & # 2 % & ! 2 % & 3 8 7 r i t e ? ! 0 2 e a d ? ! 0 data sheet 15 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.2 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following se ctions provide detailed information covering device initialization, register definition, command descript ion and device operation. 2.2.1 power on and initialization ddr2 sdram?s must be powered up an d initialized in a pred efined manner. operatio nal procedures other than those specified may result in undefined operation. power-up and init ialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 vddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. maximum power up interval for vdd / vddq is specified as 10.0 ms. th e power interval is defined as the amount of time it takes for vdd / vddq to power-up from 0 v to 2.0v +/- 0.1v for the desktop device and to 1.8 v +/- 0.1 v for the low power de vice. at least one of these two se ts of conditions must be met: ? v dd , v ddl and v ddq are driven from a single power converter output, and ? v tt is limited to 0.95 v max, and ? v ref tracks v ddq /2 ?or ?apply v dd before or at th e same time as v ddq . ?apply v ddq before or at th e same time as v tt & v ref . 2. start clock (ck, ck) and maintain stable power and clock condition for a minimum of 200 ms. 3. apply nop or deselect commands and take cke high. 4. continue nop or deselect commands for 400 ns, then issue a precharge all command. 5. issue emrs(2) command. 6. issue emrs(3) command. 7. issue emrs(1) command to enable dll. 8. issue a mrs command for ?dll reset?. 9. issue precharge-all command. 10. issue 2 or more auto-refresh commands. 11. issue the final mrs command to turn the dll on and to set the necessary operating parameter. 12. at least 200 clocks after step 8, issue emrs(1) comman ds to either execute the ocd calibration or select the ocd default. issue the final emrs(1) command to exit ocd calibration mode and set the necessary operating parameters. 13. the ddr2 sdram is now ready for normal operation. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 16 rev. 1.30, 2005-07 11222004-7n66-547b figure 4 initialization se quence after power up 2.2.2 programming the mode register and ex tended mode registers for application flexibility, bu rst length, burst type, cas latency, dll reset function, write recovery time ( t wr ) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, on die termination (odt), single-ended strobe and off chip driver impedance adjustment (ocd) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode regi ster (mrs) or extended mode registers (emrs(#)) can be altered by re- executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefined when the mrs or emrs commands are issued. also any programming of emrs(2) or emrs(3) must be followed by programming of mrs and emrs(1). after initial power up, a ll mrs and emrs commands must be issued bef ore read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. either mrs or emrs commands are activated by the low signals of cs , ras , cas and we at the positive edge of the clock. when all bank addresses ba[2:0] are low, the ddr2 sdram enables the mrs command. when the bank addresses ba0 is high and ba[2:1] are low, the ddr2 sdram enables the emrs(1) command. the address input data during this cycle defines the parameters to be set as shown in the mrs and emrs table. a new command may be issued after the mode register set command cycle time ( t mrd ). mrs, emrs and dll reset do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. 2.2.3 ddr2 sdram mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs cas latency, burst length, burst sequence, test mode, dll reset, write recovery (wr) and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba[0:1]ba[2:0], while contro lling the state of address pins a[1213:0]. the ddr2 sdram should be in all bank precharged (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time ( t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. the mode register is divided into various fields depending on functionality. burst length is defined by a[ 2:0] with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a[6:4]. a7 is used ) . ) 4 ) ! , ) : ! 4 ) / . 3 % 1 5 % . # % ! & 4 % 2 0 / 7 % 2 5 0 # , + # , + 4 4 4 4 4 4 4 4 4 % - 2 3 % - 2 3 s t ! u t o r e f r e s h n d ! u t o r e f r e s h 0 2 % ! , , - 2 3 # - $ 4 4 % - 2 3 / # $ . / 0 % - 2 3 0 2 % ! , , - 2 3 4 n s - i n c y c l e s t o l o c k t h e $ , , # + % / $ 4 u l o w h % - 2 3 / # $ ! n y # o m m a n d & o l l o w / # $ f l o w c h a r t 4 t 2 0 t - 2 3 t - 2 3 t - 2 3 t - 2 3 t 2 0 t 2 & # t 2 & # t - 2 3 t - 2 3 % x t e n d e d - o d e 2 e g i s t e r 3 e t w i t h $ , , e n a b l e - o d e 2 e g i s t e r 3 e t w i t h $ , , r e s e t - o d e 2 e g i s t e r 3 e t w o $ , , r e s e t / # $ $ r i v e o r / # $ d e f a u l t / # $ c a l i b r a t i o n m o d e e x i t data sheet 17 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description for test mode and must be set to 0 for normal dram operation. a8 is used for dll reset. a[11:9] are used for write recovery time (wr) definition for auto-precharge mode. with address bit a12 two power-down modes can be selected, a ?standard mode? and a ?low-power? power-down mode, where the dll is disabled. address bit a13 and all ?higher? address bits (including ba2) have to be set to 0 for compatibilit y with other ddr2 memory products with higher memory densities. mr mode register definition (ba[1:0] = 000 b ) ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 000 1) 1) a13 is only available for 4 and 8 configuration. pd wr dll tm cl bt bl reg. addr w w ww www field bits type 1) 1) w = write only register bits description bl [2:0] w burst length 010 4 011 8 bt 3w burst type 0 sequential 1 interleaved cl [6:4] w cas latency note: all other bit combinations are illegal. 101 5 110 6 tm 7w test mode 0 normal mode 1 vendor specific test mode dll 8w dll reset 0no 1yes wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 2 010 3 011 4 100 5 101 6 2) number of clock cycles for write recove ry during auto-precharge. wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr[cycles] t wr (ns) / t ck (ns) the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing. wr .min is determined by t ck.max and wr .max is determined by t ck.min . pd 12 w active power-down mode select 0fast exit 1 slow exit hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 18 rev. 1.30, 2005-07 11222004-7n66-547b 2.2.4 ddr2 sdram extended m ode register set (emrs(1)) the extended mode register emr(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register emr(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we , ba[2:1] and high on ba0, while controlling the st ate of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the emr(1). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.. table 7 extended mode register definition(ba[1:0] = 001 b ) ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 010 1) 1) a13 is only available for x4 and x8 commodity configurations. q off rdqs dqs ocd program rtt al rtt dic dll reg. addr ww w w w www field bits type 1) description dll 0w dll enable 0 enable 1 disable dic 1w off-chip driver impedance control 0 normal (driver size = 100%) 1 weak (driver size = 60%) r tt 2,6 w nominal termination resistance of odt note: all other bit comb inations are illegal. 00 (odt disabled) 10 75 ohm 01 150 ohm al [5:3] w additive latency note: all other bit comb inations are illegal. 000 0 001 1 010 2 011 3 100 4 ocd program [9:7] w off-chip driver calibration program 000 ocd calibration mode exit, maintain setting 001 drive (1) 010 drive (0) 100 adjust mode 111 ocd calibration default dqs 10 w complement data strobe (dqs , output) 0 enable 1 disable data sheet 19 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description a0 is used for dll enable or disable. a1 is used for e nabling half-strength data-output driver. a2 and a6 enables on-die termination (odt) and sets the rtt value. a[5:3] ar e used for additive latency settings and a[9:7] enables the ocd impedance adjustment mode. a10 enables or di sables the differential dqs and rdqs signals, a11 disables or enables rdqs. address bit a12 have to be set to 0 for normal operation. with a12 set to 1 the sdram outputs are disabled and in hi-z. 1 on ba0 and 0 for ba[2: 1] have to be set to access the emrs(1). a13 and all ?higher? address bits (inclu ding ba2) have to be set to 0 for compatibility with ot her ddr2 memory products with higher memory densities. refer to table 7 . single-ended and differential data strobe signals table 7 lists all possible combinations for dqs, dqs , rdqs, rqds which can be programmed by a[11:10] address bits in emrs(1). rdqs and rdqs are available in 8 components only. if rdqs is enabled in 8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes. dll enable/disable the dll must be enabled for high speed operation. dll enable is required dur ing power up initialization, and upon returning to normal operation after having the dll disabled. the dll is au tomatically disabled when entering self-refresh operation and is automatically re- enabled upon exit of self-refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may re sult in a violation of the t ac or t dqsck parameters. output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data (qoff bit in the emr(1) is set to 0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure idd currents during read operations, without including the output buffer current and external load currents. rdqs 11 w read data strobe output (rdqs, rdqs ) 0 disable 1 enable qoff 12 w output disable 0 output buffers enabled 1 output buffers disabled 1) w = write only register bits field bits type 1) description (cont?d) table 8 single-ended and differential data strobe signals emrs(1) strobe function matrix signaling a11 (rdqs enable) a10 (dqs enable) rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs rdqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 20 rev. 1.30, 2005-07 11222004-7n66-547b 2.2.5 emrs(2) the extended mode registers emrs(2) and emrs(3) are reserved for future use and must be programmed when setting the mode register during initialization. the extended mode register(2) controls refresh related features. the default value of the extended mode reg- ister(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper operation. the extended mode register emrs(2) is written by asserting low on cs , ras , cas , we , ba2, ba0 and high on ba1,while controlling the states of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register(2). the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the extended mode register(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. 2.2.6 emrs(3) the extended mode register emr(3) is reserved for future use and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. 2.3 off-chip driver (ocd ) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) should be carefully controlled depending on system environment. emrs(2) programming extended mode register definition (ba[1:0] = 01 b ) ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 10 0 1)2) 1) a13 is only available for x4 and x8 commodity configurations. 2) must be programmed to ?0? reg.addr emr(3) programming extended mode register definition (ba[1:0] = 01 b ) ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 11 0 1)2) 1) a13 is only available for x4 and x8 commodity configurations. 2) must be programmed to ?0? reg. addr data sheet 21 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 5 ocd impedance adjustment flow chart note 1. mr should be set before entering ocd impedance adju stment odt should be carefully controlled depending on system environment mpft0020 start emrs: ocd calibration mode exit need calibration emrs: enter adjust mode bl = 4 code input to all dqs inc, dec or nop emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: drive (1) dq & dqs high; dqs low all ok emrs: drive (0) dq & dqs low; dqs high test test emrs: ocd calibration mode exit emrs: enter adjust mode bl = 4 code input to all dqs inc, dec or nop need calibration emrs: ocd calibration mode exit emrs: ocd calibration mode exit end all ok hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 22 rev. 1.30, 2005-07 11222004-7n66-547b 2.3.1 extended mode register se t for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs(1) mode. in dr ive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emr(1) bit enabling rdqs operation. in drive(1) mode, all dq, dqs (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. in drive(0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs (and rdqs ) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characterist ics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in table 10 . ocd applies only to normal full strength output drive setting defined by emr(1) and if half strength is set, ocd default output driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is comp leted or driver strength is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a[9:7] as ?000? in order to maintain the default or calibrated value. ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs(1) command along with a 4 bit burst code to ddr2 sdram as in table 10 . for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 in table 10 means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdra m dqs simultaneously and after ocd calibration, all dq s of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maximum step count range. when adjust mode command is issued, al from previously set value must be applied. table 9 output driver character istics for ocd calibration a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs (rdqs) high 1 0 0 adjust mode 1 1 1 ocd calibration default table 10 off- chip-dri ver adjust program 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0 000nop (no operation) nop (no operation) 0 001increase by 1 step nop 0 010decrease by 1 step nop 0 100nop increase by 1 step 1 000nop decrease by 1 step 0 101increase by 1 step increase by 1 step 0 110decrease by 1 step increase by 1 step 1 001increase by 1 step decrease by 1 step 1 010decrease by 1 step decrease by 1 step other combinations illegal data sheet 23 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds / t dh should be met as figure 6 . input data pattern for adjustment, dt[0:3] is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). burst length of 4 have to be programmed in the mrs for ocd impedance adjustment. figure 6 adjust mode timing diagram drive mode both drive(1) and drive(0) are used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command. see figure 7 . figure 7 drive mode timing diagram ! $ * 5 3 4 - / $ % 4 ) - ) . ' # , + # , + . / 0 . / 0 . / 0 . / 0 % - 2 3 . / 0 $ 4 $ 4 $ 4 $ 4 # - $ $ 1 3 $ 1 3 $ 1 . / 0 . / 0 . / 0 % - 2 3 . / 0 7 , t 7 2 $ - t $ 3 t $ ( / # $ a d j u s t m o d e / # $ c a l i b r a t i o n m o d e e x i t $ 2 ) 6 % - / $ % 4 ) - ) . ' # , + # , + . / 0 . / 0 % - 2 3 . / 0 # - $ $ 1 3 i n $ 1 i n . / 0 . / 0 . / 0 % - 2 3 . / 0 ) / ) 4 ) / ) 4 % n t e r $ r i v e - o d e / # $ c a l i b r a t i o n m o d e e x i t $ 1 3 h i g h $ 1 3 l o w f o r $ r i v e $ 1 3 l o w $ 1 3 h i g h f o r $ r i v e $ 1 3 h i g h f o r $ r i v e $ 1 3 h i g h f o r $ r i v e hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 24 rev. 1.30, 2005-07 11222004-7n66-547b 2.4 on-die termination (odt) on-die terminatio n (odt) is a new feature on ddr2 components that allows a dram to turn on/off termi- nation resistance for each dq, dqs, dqs , dm for 4 and dq, dqs, dqs , dm, rdqs (dm/rdqs share the same pin) and rdqs for 8 configuration via the odt control pin. dqs and rdqs are only terminated when enabled by emr(1). for 16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resis- tance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self-refresh mode. figure 8 functional representation of odt switch sw1 or sw2 is enable d by the odt pin. selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target rtt = 0.5 rval1 or 0.5 rval2 . the odt pin will be ignored if the extended mode register (emrs(1)) is programmed to disable odt. dram input buffer input pin rval1 rval1 rval2 rval2 sw1 sw1 sw2 sw2 vddq vddq vssq vssq data sheet 25 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description odt truth tables the odt truth table shows wh ich of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs(1). to activate termination of any of these pins, the odt functi on has to be enabled in the emrs(1) by address bits a6 and a2. note: x = don?t care; 0 = bit se t to low; 1 = bit set to high odt timing modes depending on the operating mode synchronous or asynchronous odt timings apply. asynchronous odt timings ( t aofpd , t aonpd ) apply when the on-die dll is disabled. these modes are: ? slow exit active power down mode (with mrs bit a12 is set to ?1?) ? precharge power down mode synchronous odt timings ( t aond , t aofd, t aon, t aof, ) apply for all other modes. figure 9 odt timing for active and standby (idle) modes (synchronous odt timings) note: table 11 odt truth table input pin emrs(1) address bit a10 emrs(1) address bit a11 16 components dq[15:0] x ldqs x ldqs 0 udqs x x udqs 0 ldm x x udm x x / $ 4 4 ) - ) . ' & / 2 ! # 4 ) 6 % ! . $ 3 4 ! . $ " 9 ) $ , % - / $ % 3 3 9 . # ( 2 / . / 5 3 / $ 4 4 ) - ) . ' 3 # , + # , + 4 4 4 4 4 4 4 4 4 4 / $ 4 $ 1 t ! / . $ t # + 4 4 # + % 2 t t t ! / & $ t # + t t t t ! / . m i n t ! / . m a x t ! / & m i n t ! / & m a x hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 26 rev. 1.30, 2005-07 11222004-7n66-547b 1. synchronous odt timings apply for active mode and standby mode with cke high and for the ?fast exit? active power down mode (mrs bit a12 set to ?0?). in all these modes the on-die dll is enabled. 2. odt turn-on time ( t aon,min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. ( t aon max ) is when the odt resistance is fully on. both are measured from t a ond . 3. odt turn off time min. ( t aof min ) is when the device starts to turn off the od t resistance.odt turn off time max. ( t aof max ) is when the bus is in high impedance. both are measured from t aofd . figure 10 odt timing for precharge power-down and active power-down mode (with slow exit) (asynchronous odt timings) note: asynchronous odt timings apply for precharge po wer-down mode and ?slow exit? active power down mode (mrs bit a12 set to ?1?), where the on-die dll is disabled in this mode of operation. mode entry: as long as the timing parameter t anpd, min is satisfied when odt is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. if t anpd, min is not satisfied, asynchronous timing parameters apply. / $ 4 4 ) - ) . ' & / 2 0 2 % # ( ! 2 ' % 0 / 7 % 2 $ / 7 . ! . $ ! # 4 ) 6 % 0 / 7 % 2 $ / 7 . - / $ % 7 ) 4 ( 3 , / 7 % 8 ) 4 ! 3 9 . # ( 2 / . / 5 3 / $ 4 4 ) - ) . ' 3 # , + # , + 4 4 4 4 4 4 4 4 4 4 / $ 4 $ 1 t ! / . 0 $ m i n 4 4 # + % 2 t t t ! / & 0 $ m a x t t u l o w h t ! / . 0 $ m a x t ! / & 0 $ m i n data sheet 27 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 11 odt mode entry timing diagram mode exit: as long as the timing parameter t axpd, min is satisfied when odt is turned on or off after exiting these power- down modes, synchronous timing parameters can be applied. if t axpd, min is not satisfied, asynchronous timing parameters apply. / $ 4 - / $ % % . 4 2 9 4 ) - ) . ' $ ) ! ' 2 ! - # , + # , + t 3 y n c h r o n o u t i m i n g s a p p l y 2 4 4 4 4 4 4 4 4 4 4 # + % / $ 4 2 4 4 / $ 4 t ! / & $ t ! / & & $ m a x t ! . 0 $ t # + t / $ 4 t ! / . $ 2 4 4 t / $ 4 t ! / . 0 $ m a x 2 4 4 t ! s y n c h r o n o u t i m i n g s a p p l y 3 y n c h r o n o u t i m i n g s a p p l y ! s y n c h r o n o u t i m i n g s a p p l y / $ 4 t u r n o f f t ! . 0 $ t # + / $ 4 t u r n o f f t ! . 0 $ t # + / $ 4 t u r n o f f t ! . 0 $ t # + / $ 4 t u r n o f f t ! . 0 $ t # + hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 28 rev. 1.30, 2005-07 11222004-7n66-547b figure 12 odt mode exit timing diagram / $ 4 - / $ % % 8 ) 4 4 ) - ) . ' $ ) ! ' 2 ! - # , + # , + t ) 3 3 y n c h r o n o u t i m i n g s a p p l y 2 4 4 # + % / $ 4 2 4 4 / $ 4 t ) 3 t ! / & & $ m a x t ! 8 0 $ t ) 3 / $ 4 t ! / . $ 2 4 4 t ) 3 / $ 4 t ! / . 0 $ m a x 2 4 4 t ! s y n c h r o n o u t i m i n g s a p p l y / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n 4 4 4 4 4 4 4 4 / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n 3 y n c h r o n o u t i m i n g s a p p l y ! s y n c h r o n o u t i m i n g s a p p l y / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n data sheet 29 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.5 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank ad dresses ba[1:0][2:0] are used to select the desired bank. the row addresses a0 through a1213 are used to determine which row to activate in the selected bank for 4 and 8 organized components. for 16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd.min specification, then additive latency must be programmed into the device to delay the r/w command which is inte rnally issued to the device. the additive latency value must be chosen to assure t rcd.min is satisfied. additive latencies of 0, 1, 2, 3 and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined by t rc . the minimum time interval between bank active commands to different banks is t rrd . figure 13 bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2 2.6 read and write comma nds and access modes after a bank has been activa ted, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will in itiate a serial read or write operation on successive clock cycles. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 16mbit 16 chip has a page size of 20481024 kbyte which corresponds to a page length of 1024512 bits (defined by ca[8:0]). in case of a 4-bit burst operation (burst length = 4) the page length of 512 is divided into 128 uniquely addressable segments (4-bits 1616 i/o each). the 4- bit burst operation will occur entirely within one of the 128 segments (defined by ca [6:0]) starting with the column address supplied to the device during the read or write command (ca[8:0]). the second, third and fourth access will also o ccur within this segment, however, the burst order is a function of the starting address, and the burst sequence. " ! . + ! # 4 ) 6 ! 4 % # / - - ! . $ # 9 # , % # , + # , + 4 4 4 4 n 4 n " a n k ! 2 o w ! d d r " a n k ! ! d d r . / 0 " a n k " ! d d r ! d d 4 " a n k ! ! c t i v a t e 0 o s t e d # ! 3 2 e a d ! " a n k " ! c t i v a t e 0 o s t e d # ! 3 2 e a d " " a n k ! 0 r e c h a r g e . / 0 # - $ " a n k ! # o l ! d d r " a n k " 2 o w ! d d r " a n k " # o l ! d d r 4 " a n k ! 2 o w ! d d r " a n k " 0 r e c h a r g e " a n k ! ! c t i v a t e 4 n 4 n ) n t e r n a l 2 ! 3 # ! 3 d e l a y t 2 # $ m i n " a n k ! t o " a n k " d e l a y t 2 2 $ ! d d i t i v e l a t e n c y ! , 2 e a d ! " e g i n s t 2 ! 3 2 o w ! c t i v e 4 i m e " a n k ! t 2 0 2 o w 0 r e c h a r g e 4 i m e " a n k ! t # # $ t 2 # 2 o w # y c l e 4 i m e " a n k ! hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 30 rev. 1.30, 2005-07 11222004-7n66-547b in case of a 8-bit burst operation (burst length = 8) the page length of 512 is divided into 64 uniquely addressable segments (8-bits 16 i/o each). the 8-bit burst operation will occur enti rely within one of the 64 segments (defined by ca[5:0]) beginning with the column address supplied to the device during the read or write command (ca[8:0]). a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay ( t ccd ) is a minimum of 2 clocks for read or write cycles. for 8 bit burst operation (bl = 8) the minimum cas to cas delay ( t ccd ) is 4 clocks for read or write cycles. burst interruption is allowed with 8 bit burst operation. for details see chapter 2.6.6 . figure 14 read burst timing example: (c l = 5, al = 0, rl = 5, bl = 4) 2.6.1 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this o peration, the ddr2 sdram allows a read or write command to be issued immediately after the ras ba nk activate command (or any time during the ras to cas delay time, t rcd period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the t rcd, min , then al greater than 0 must be written into the emrs(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcd, min period, the read latency is also defined as rl = al + cl. 2 % ! $ " 5 2 3 4 4 ) - ) . ' % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 2 % ! $ ! . / 0 2 % ! $ " . / 0 2 % ! $ # . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! $ o u t " $ o u t " $ o u t " $ o u t " $ o u t # $ o u t # $ o u t # $ o u t # # - $ $ 1 3 $ 1 3 $ 1 t # # $ t # # $ . / 0 4 4 data sheet 31 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 15 activate to read timing exampl e: read followed by a write to the same bank, activate to read delay < t rcdmin : al = 2 and cl = 5, rl = (al + cl) = 7, wl = (rl -1) = 6, bl = 4 figure 16 read to write timing example: read followed by a write to the same bank, activate to read delay < t rcdmin : al = 2 and cl = 5, rl = (al + cl) = 7, wl = (rl -1) = 6, bl = 8 figure 17 read to write timing example: read followed by a write to the same bank, activate to read delay = t rcdmin : al = 0, cl = 5, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 ! # 4 ) 6 ! 4 % 4 / 2 % ! $ 4 ) - ) . ' % 8 ! - 0 , % # , + # , + $ o u t $ o u t $ o u t $ o u t # - $ $ 1 3 $ 1 3 $ 1 ! , # , ! c t i v a t e " a n k ! 2 e a d " a n k ! 7 r i t e " a n k ! $ i n $ i n $ i n $ i n t 2 # $ 2 , ! , # , 7 , 2 , 2 % ! $ 4 / 7 2 ) 4 % 4 ) - ) . ' % 8 ! - 0 , % ? & ) ' 5 2 % ? # , + # , + $ o u t $ o u t $ o u t $ o u t # - $ $ 1 3 $ 1 3 $ 1 ! , # , ! c t i v a t e " a n k ! 2 e a d " a n k ! 7 r i t e " a n k ! $ i n t 2 # $ 2 , ! , # , 7 , 2 , $ o u t $ o u t $ o u t $ o u t $ i n 2 % ! $ 4 / 7 2 ) 4 % 4 ) - ) . ' % 8 ! - 0 , % ? & ) ' 5 2 % ? # , + # , + $ o u t $ o u t $ o u t $ o u t # - $ $ 1 3 $ 1 3 $ 1 ! , # , ! c t i v a t e " a n k ! 2 e a d " a n k ! 7 r i t e " a n k ! $ i n t 2 # $ 2 , ! , # , 7 , 2 , $ i n hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 32 rev. 1.30, 2005-07 11222004-7n66-547b figure 18 read to write timing example: read followed by a write to the same bank, activate to read delay > t rcdmin : al = 1, cl = 5, rl = 6, wl = 5, bl = 4 2 % ! $ 4 / 7 2 ) 4 % 4 ) - ) . ' % 8 ! - 0 , % ? & ) ' 5 2 % ? # , + # , + $ o u t $ o u t $ o u t $ o u t # - $ $ 1 3 $ 1 3 $ 1 ! c t i v a t e " a n k ! 2 e a d " a n k ! 7 r i t e " a n k ! $ i n t 2 # $ t 2 # $ m i n 2 , 7 , $ i n $ i n $ i n data sheet 33 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.6.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory location s (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a[2:0] of the mr. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mr. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the chapter 2.6.6 . a burst stop command is not supported on ddr2 sdram devices. notes ? page size for all 256 mbit components is 1 kbyte page size and length is a function of i/o organization: 64 mb 16 organization (ca[8:0]); page si ze = 1 kbyte; page length = 512 4. order of burst access for sequential addressing is ?n ibble-based? and therefore different from sdr or ddr components table 12 burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 0 1 1, 2, 3, 0 1, 0, 3, 2 0 1 0 2, 3, 0, 1 2, 3, 0, 1 0 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 34 rev. 1.30, 2005-07 11222004-7n66-547b 2.6.3 read command the read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address in puts determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs(1)). figure 19 basic read timing diagram figure 20 read operation example 1: rl = 7 (al = 2, cl = 5, bl = 4) the seamless read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or diff erent banks as long as the banks are activated. " ! 3 ) # 2 % ! $ 4 ) - ) . ' $ ) ! ' 2 ! - $ o u t $ 1 3 $ 1 3 $ 1 t , : # , + # , + t # ( t # , t # + t $ 1 3 # + t ! # t 2 0 2 % t 1 ( t $ 1 3 1 m a x $ o u t $ o u t $ o u t t 2 0 3 4 t ( : t $ 1 3 1 m a x t 1 ( " 5 2 3 4 / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 0 o s t # ! 3 2 e a d ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 $ 1 ! , # , . / 0 4 4 2 , t $ 1 3 # + 4 4 4 data sheet 35 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 21 read operation example 2: rl = 5 (al = 0, cl = 5, bl = 8) figure 22 read followed by write example: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the read command to the write co mmand is defined by a read-to-write turn-around time, which is bl/2 + 2 clocks. figure 23 seamless read operation example 1: rl = 7, al = 2, cl = 5, bl = 4 2 % ! $ / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 2 e a d ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 $ 1 # , . / 0 4 4 2 , t $ 1 3 # + $ o u t ! $ o u t ! $ o u t ! $ o u t ! 2 % ! $ & / , , / 7 % $ " 9 7 2 ) 4 % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 0 o s t e d # ! 3 7 r i t e ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 $ 1 " , . / 0 4 2 , 4 $ i n ! $ i n ! $ i n ! $ i n ! 7 , 2 , 3 % ! - , % 3 3 2 % ! $ / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 0 o s t e d # ! 3 2 a e d ! . / 0 0 o s t e d # ! 3 7 r i t e ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 $ 1 4 4 2 , $ o u t " $ o u t " $ o u t " $ o u t " ! , # , . / 0 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 36 rev. 1.30, 2005-07 11222004-7n66-547b the seamless read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or diff erent banks as long as the banks are activated. figure 24 seamless read operation example 2: rl = 5, al = 0, cl = 5, bl = 8 (non interrupting) the seamless, non interrupting 8-bit read operation is supported by enabling a read command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. 3 % ! - , % 3 3 2 % ! $ / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 0 o s t e d # ! 3 2 a e d ! . / 0 0 o s t e d # ! 3 7 r i t e ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 $ 1 4 4 2 , $ o u t " $ o u t " $ o u t " $ o u t " # , . / 0 $ o u t " $ o u t " $ o u t " $ o u t " $ o u t ! $ o u t ! $ o u t ! $ o u t ! data sheet 37 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.6.4 write command the write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl - 1). a data strobe signal (dqs) has to be driven low (preamble) a time t wpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from th e completion of the burst write to bank precharge is named ?write recovery time? ( t wr ) and is the time needed to store the write data into the memory array. t wr is an analog timing parameter (see electrical characteristics ) and is not the programmed value for wr in the mrs. figure 25 basic write timing figure 26 write operation example 1: rl = 7 (al = 2, cl = 5), wl = 4, bl = 4 " ! 3 ) # 7 2 ) 4 % 4 ) - ) . ' $ i n $ 1 3 $ 1 3 $ 1 t $ 1 3 ( $ i n $ i n $ i n t $ 1 3 ( t 7 0 2 % t $ 3 t $ ( t 7 0 3 4 7 2 ) 4 % / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 0 o s t # ! 3 7 r i t e ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 0 r e c h a r g e 4 4 7 , 2 , $ 1 3 3 t 7 2 # o m p l e t i o n o f t h e " u r s t 7 r i t e hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 38 rev. 1.30, 2005-07 11222004-7n66-547b figure 27 write operation example 2: rl = 5 (al = 0, cl = 5), wl = 2, bl = 4 figure 28 write followed by read example: rl = 7 (al = 2, cl = 5), wl = 4, t wtr = 2, bl = 4 the minimum number of clocks from the write command to the read command is (cl - 1) +bl/2 + t wtr , where t wtr is the write-to-read turn-around time t wtr expressed in clock cycles. the t wtr is not a write recovery time ( t wr ) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. 7 2 ) 4 % / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 0 o s t # ! 3 7 r i t e ! . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 " a n k ! ! c t i v a t e $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 0 r e c h a r g e 4 4 7 , 2 , $ 1 3 3 t 7 2 # o m p l e t i o n o f t h e " u r s t 7 r i t e t 2 0 7 2 ) 4 % & / , , / 7 % $ " 9 2 % ! $ % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 4 4 7 , 2 , ! , # , t 7 4 2 2 , . / 0 . / 0 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 7 r i t e t o 2 e a d # , " , t 7 4 2 data sheet 39 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 29 seamless write operation example 1: rl = 5, wl = 4, bl = 4 the seamless write operation is supported by enablin g a write command every bl/2 number of clocks. this operation is allowed regardless of same or diff erent banks as long as the banks are activated. figure 30 seamless write operation example 2: rl = 3, wl = 4, bl = 8, non interrupting the seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. 3 % ! - , % 3 3 7 2 ) 4 % / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 4 4 7 , 2 , . / 0 . / 0 . / 0 0 o s t e d # ! 3 7 r i t e ! 0 o s t e d # ! 3 7 r i t e " $ i n " $ i n " $ i n " $ i n " 3 % ! - , % 3 3 7 2 ) 4 % / 0 % 2 ! 4 ) / . % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 7 r i t e " . / 0 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 4 4 7 , 2 , . / 0 . / 0 . / 0 7 r i t e ! $ i n " $ i n " $ i n " $ i n " . / 0 $ i n " $ i n " $ i n " $ i n " $ i n ! $ i n ! $ i n ! $ i n ! 4 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 40 rev. 1.30, 2005-07 11222004-7n66-547b 2.6.5 write data mask two write data mask inputs (ldm, udm)are supported on ddr2 sdram?s , consistent with the implementation on ddr sdram?s. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, the write data bit is not written to the memory. figure 31 write data mask timing figure 32 write operation with data mask exam ple: rl = 5 (al = 0, cl = 5), wl = 4, t wr = 3, bl = 4 7 2 ) 4 % $ ! 4 ! - ! 3 + 4 ) - ) . ' $ $ 1 3 $ 1 3 $ 1 t $ 1 3 ( $ $ $ - a s k - a s k - a s k - a s k $ - d o n | t c a r e t $ 1 3 ( t 7 0 2 % t $ 3 t $ ( t 7 0 3 4 7 2 ) 4 % / 0 % 2 ! 4 ) / . 7 ) 4 ( $ ! 4 ! - ! 3 + % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 0 r e c h a r g e $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 $ 1 4 4 7 , 2 , . / 0 " a n k ! ! c t i v a t e . / 0 7 r i t e ! . / 0 4 t $ 1 3 3 t 7 2 t 2 0 $ - data sheet 41 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.6.6 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. figure 33 read interrupt timing example 1: (cl = 5, al = 0, rl = 5, bl = 8) figure 34 write interrupt timing example 2: (cl = 5, al = 0, wl = 4, bl = 8) 2 % ! $ ) . 4 % 2 2 5 0 4 4 ) - ) . ' % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 . / 0 . / 0 2 e a d ! 2 e a d " $ o u t " $ o u t " $ o u t " $ o u t " $ 1 $ o u t " $ o u t " $ o u t " $ o u t " 4 7 2 ) 4 % ) . 4 % 2 2 5 0 4 4 ) - ) . ' % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 4 4 . / 0 . / 0 . / 0 7 r i t e ! 7 r i t e " $ i n " $ i n " $ i n " $ i n " $ 1 $ i n " $ i n " $ i n " $ i n " 4 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 42 rev. 1.30, 2005-07 11222004-7n66-547b 2.7 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre- charge command can be used to precharge each bank independently or all bank s simultaneously. three address bits a10, ba0 and ba[2:1] are used to define which bank to precharge when the command is issued. note: the bank address assignment is the same for activating and precharging a specific bank. 2.7.1 read operation followed by a precharge the following rules apply as long as the t rtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 mhz (ddr2 400 and 533 speed sorts): minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read command, as long as the minimum t ras timing is satisfied. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the precharge begins. 2. the ras cycle time ( t rc, min ) from the previous bank activation has been satisfied. figure 35 read operation followed by precharge example 1: rl = 6 (al = 1, cl = 5), bl = 4, t rtp 2 clocks table 13 bank selection for precharge by address bits a10 ba0 ba1 precharge bank(s) low 0 0 bank 0 only low 0 1 bank 1 only low 1 0 bank 2 only low 1 1 bank 3 only high don?t care don?t care all banks 2 % ! $ / 0 % 2 ! 4 ) / . & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 " a n k ! ! c t i v a t e . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 0 r e c h a r g e $ 1 4 ! , " , c l k s ! , # , 2 , t 2 0 t 2 ! 3 t 2 # t 2 4 0 data sheet 43 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 36 read operation followed by precharge example 2: rl = 6 (al = 1, cl = 5), bl = 8, t rtp 2 clocks figure 37 read operation followed by precharge example 3: rl = 7 (al = 2, cl = 5), bl = 4, t rtp 2 clocks 2 % ! $ / 0 % 2 ! 4 ) / . & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 " a n k ! ! c t i v a t e . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 0 r e c h a r g e $ 1 4 ! , " , c l k s ! , # , 2 , t 2 0 t 2 ! 3 t 2 # t 2 4 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! & i r s t b i t p r e f e t c h 3 e c o n d b i t p r e f e t c h 2 % ! $ / 0 % 2 ! 4 ) / . & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 " a n k ! ! c t i v a t e $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 0 r e c h a r g e $ 1 4 ! , " , c l k s ! , # , 2 , t 2 0 t 2 ! 3 t 2 # t 2 4 0 . / 0 . / 0 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 44 rev. 1.30, 2005-07 11222004-7n66-547b figure 38 read operation followed by precharge example 4: rl = 7, (al = 2, cl = 5), bl = 4, t rtp 2clocks 2 % ! $ / 0 % 2 ! 4 ) / . & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 " a n k ! ! c t i v a t e $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d ! . / 0 . / 0 0 r e c h a r g e ! $ 1 4 ! , " , c l k s ! , # , 2 , t 2 0 t 2 ! 3 t 2 # t 2 4 0 . / 0 . / 0 data sheet 45 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.7.2 write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is know n as a write recovery time ( t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see chapter 7 ) and is not the programmed value for wr in the mrs. figure 39 write followed by precharge exam ple 1: wl = (rl - 1) = 4, bl = 4, t wr = 3 figure 40 write followed by precharge exam ple 2: wl = (rl - 1) = 4, bl = 4, t wr = 3 7 2 ) 4 % & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 7 r i t e ! . / 0 . / 0 0 r e c h a r g e ! $ 1 4 7 , t 7 2 . / 0 . / 0 # o m p l e t i o n o f t h e " u r s t 7 r i t e 7 2 ) 4 % & / , , / 7 % $ " 9 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 7 r i t e ! . / 0 . / 0 0 r e c h a r g e ! $ 1 4 7 , t 7 2 . / 0 . / 0 # o m p l e t i o n o f t h e " u r s t 7 r i t e hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 46 rev. 1.30, 2005-07 11222004-7n66-547b 2.8 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precha rged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then the auto-precharge function is enabled. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto-precharge is also implemented for write commands.the precharge operation engaged by the auto-precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge command may be issued with any read or write command. 2.8.1 read with auto-precharge if a10 is 1 when a read command is issued, the read with auto-precharge func tion is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles la ter from the read with ap command if t ras(min) and t rtp are satisfied. if t ras(min) is not satisfied at the edge, the start point of auto-precharge op eration will be delayed until t ras(min) is satisfied. if t rtpmin is not satisfied at the edge, the start point of auto -precharge operation will be delayed until t rtpmin is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + t rtp + t rp . note that ( t rtp + t rp ) has to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the auto-precharge begins. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. data sheet 47 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 41 read with auto-precharge example 1, followed by an activation to the same bank ( t rc limit): rl = 7 (al = 2, cl = 5), bl = 4, t rtp 2 clocks figure 42 read with auto-precharge example 2, fo llowed by an activation to the same bank ( t ras limit): rl = 7 (al = 2, cl = 5), bl = 4, t rtp 2 clocks 2 % ! $ 7 ) 4 ( ! 5 4 / 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d w ! 0 . / 0 . / 0 " a n k ! c t i v a t e $ 1 4 ! , t 2 0 . / 0 . / 0 # , ! u t o 0 r e c h a r g e " e g i n s 2 , ! , " , t 2 ! 3 t 2 # m i n ! u h i g h h 2 % ! $ 7 ) 4 ( ! 5 4 / 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d w ! 0 . / 0 . / 0 " a n k ! c t i v a t e $ 1 4 ! , t 2 0 . / 0 . / 0 # , ! u t o 0 r e c h a r g e " e g i n s 2 , t 2 # ! u h i g h h t 2 ! 3 m i n hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 48 rev. 1.30, 2005-07 11222004-7n66-547b figure 43 read with auto-precharge example 3, followed by an activation to the same bank: rl = 6 (al = 1, cl = 5), bl = 8, t rtp 2 clocks 2 % ! $ 7 ) 4 ( ! 5 4 / 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 4 4 4 4 . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 4 . / 0 0 o s t e d # ! 3 2 e a d w ! 0 . / 0 . / 0 " a n k ! c t i v a t e $ 1 4 ! , t 2 0 . / 0 . / 0 # , ! u t o 0 r e c h a r g e " e g i n s 2 , ! , " , t 2 4 0 ! a h i g h $ o u t ! $ o u t ! $ o u t ! $ o u t ! & i r s t b i t p r e f e t c h 3 e c o n d b i t p r e f e t c h data sheet 49 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.8.2 write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the write burst plus the write recovery time delay ( t wr ), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. 1. the last data-in to bank activate delay time ( t dal = wr + t rp ) has been satisfied. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. in ddr2 sdram?s the write recovery time delay ( t wr ) has to be programmed into the mrs mode register. as long as the analog t wr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + t dal . figure 44 write with auto-precharge example 1 ( t rc limit): wl = 4, t dal = 6 (wr = 3, t rp = 3), bl = 4 figure 45 write with auto-precharge example 2 (wr + t rp limit): wl = 4, t dal = 6 (wr = 3, t rp = 3), bl = 4 7 2 ) 4 % 7 ) 4 ( ! 5 4 / 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 7 r i t e w ! 0 . / 0 " a n k ! c t i v a t e $ 1 t 2 0 . / 0 . / 0 # o m p l e t i o n o f t h e " u r s t 7 r i t e 7 , 2 , t 2 ! 3 m i n t 2 # m i n ! u h i g h h 4 7 2 t $ ! , ! u t o 0 r e c h a r g e " e g i n s 4 4 4 7 2 ) 4 % 7 ) 4 ( ! 5 4 / 0 2 % # ( ! 2 ' % % 8 ! - 0 , % # , + # , + 4 4 4 4 4 . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 0 o s t e d # ! 3 7 r i t e w ! 0 . / 0 . / 0 " a n k ! c t i v a t e $ 1 t 2 0 . / 0 . / 0 # o m p l e t i o n o f t h e " u r s t 7 r i t e 7 , 2 , t 2 ! 3 t 2 # ! u h i g h h 4 7 2 t $ ! , ! u t o 0 r e c h a r g e " e g i n s 4 4 4 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 50 rev. 1.30, 2005-07 11222004-7n66-547b 2.8.3 read or write to pr echarge command spacing summary the following table summarizes the minimum command delays between read, read w/ap, write, write w/ap to the precharge commands to the same banks and precharge-all commands. 2.8.4 concurrent auto-precharge ddr2 devices support the ?concurrent auto- precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus. the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in table 15 . as defined, the wl = rl - 1 for ddr2 devices which allows the command gap and corresponding data gaps to be minimized. table 14 minimum command delays from command to command minimum delay between ?from command? to ?to command? units notes read precharge (to same banks as read) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) 1) ru{ t rtp (ns) / t ck (ns)} must be used, where ru stands for ?round up? 2) for a given bank, the precharge period shoul d be counted from the latest precharge command, either one bank precharge or precha rge- all, issued to that bank. the pr echarge period is satisfied after t rp or t rp, all depending on the latest precharge command issued to that bank precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) read w/ap precharge (to same banks as read w/ap) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) write precharge (to same banks as write) wl + bl/2 + t wr t ck 2)3) 3) ru{ t wr (ns) / t ck (ns)} must be used, where ru stands for ?round up? precharge-all wl + bl/2 + t wr t ck 2)3) write w/ap precharge (to same banks as write w/ap) wl + bl/2 + wr t ck 2) precharge-all wl + bl/2 + wr t ck 2) precharge precharge (to same banks as precharge) 1 t ck 2) precharge-all 1 t ck 2) precharge-all precharge 1 t ck 2) precharge-all 1 t ck 2) data sheet 51 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.9 refresh ddr2 sdram requires a refresh of all rows of a bank withi n a time interval defined by 8192 (which represents the number of rows) x t refi . the necessary refresh can be generated in one of two ways: by explicit auto-refresh commands or by an internally timed self-refresh mode. 2.9.1 auto-refresh command auto-refresh is used during normal operation of the ddr2 sdram?s. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generat ed by the internal refresh controller. this makes the address bits ?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of t ref(maximum) . when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time ( t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharg ed (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto- refresh cycle time ( t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 t refi . figure 46 auto refresh timing table 15 command delay table from command to command (different bank, non-interrupting command) minimum delay with concurrent auto- precharge support units note write w/ap read or read w/ap (cl -1) + (bl/2) + t wtr t ck 1) 1) ru{t wtr (ns)/t ck (ns)} must be used where ru stands for ?round up? write or write w/ap bl/2 t ck precharge or activate 1 t ck 2) 2) this rule only applies to a selective precharge comm and to another banks, a precharge-all command is illegal read w/ap read or read w/ap bl/2 t ck write or write w/ap bl/2 + 2 t ck precharge or activate 1 t ck 2) ! 5 4 / 2 % & 2 % 3 ( 4 ) - ) . ' # , + # , + 4 4 4 . / 0 . / 0 . / 0 # - $ # + % 0 r e c h a r g e ! u t o 2 e f r e s h . / 0 ! . 9 4 . / 0 ! u t o 2 e f r e s h u h i g h h t 2 0 t 2 & # t 2 & # hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 52 rev. 1.30, 2005-07 11222004-7n66-547b 2.9.2 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self- refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs(1) command. once the command is registered, cke must be held low to keep the de vice in self-refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self- refresh mode all of the external control signals, except cke, are ?don?t care?. the dram initiates a minimum of one auto refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during self-refresh operation to save power. the minimum time that the ddr2 sdram must remain in se lf refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high . once self-refresh exit command is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self-refresh exit period t xsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after t xsnr expires. nop or deselect commands must be registered on each positive clock edge during the self-ref resh exit interval t xsnr . odt should be turned off during t xsnr . the use of self refresh m ode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. figure 47 self refresh timing note: 1. device must be in the ?all banks idle? state before entering self refresh mode. 2. t xsrd ( 200 t ck ) has to be satisfied for a read or a read with auto-precharge command. 3. t xsnr has to be satisfied for any command except a read or a read with auto-precharge command 4. since cke is an sstl input, v ref must be maintained during self refresh. 3 % , & 2 % & 2 % 3 ( 4 ) - ) . ' # , + # , + 4 4 4 4 4 4 m 4 n 4 r # + % t ) 3 / $ 4 3 e l f 2 e f r e s h % n t r y . / 0 . o n 2 e a d # o m m a n d # - $ 2 e a d # o m m a n d 4 t ! / & $ t ) 3 t 2 0 t ) 3 t # + % t 8 3 2 $ t 8 3 . 2 data sheet 53 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.10 power-down power-down is synchronous ly entered when cke is registered low, along with nop or deselect command. cke is not allowed to go lo w while mode register or extended mode register command time, or read or write operation is in progress. c ke is allowed to go low while any other operation such as row activation, precharge, auto-precharge or auto-refresh is in progress, but power-down i dd specification will no t be applied until finishing those operations. the dll should be in a locked state when power-down is entered. otherwise dll shoul d be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with any cke intensive operations as long as dram controller complies with dram specifications. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to ?low? this mode is referred as ?standard active power-down mode? and a fast power-down exit ti ming defined by the t xard timing parameter can be used. when a12 is set to ?high? this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-down, but the dll is kept enabled during fast exit active power-down. in power- down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down duration is limited by 9 times t refi of the device. the power-down state is synchronously exited when cke is registered high (a long with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defined in table 44 and ff. power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power- mode after an auto-refresh command or mrs / emrs(1) command when t mrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode en try after a read or read with auto-precharge comma nd is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active power- down mode entry is allowed when wl + bl/2 + t wtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is wl + bl/2 + wr starting from the write with auto- precharge command. in this case the ddr2 sdram enters the precharge power-down mode. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 54 rev. 1.30, 2005-07 11222004-7n66-547b figure 48 active power-down mode entry and exit after an activate command note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. figure 49 active power-down mode entry and exit example after a read command: rl = 6 (al = 1, cl =5), bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. ! # 4 ) 6 0 / 7 % 2 $ / 7 . - / $ % % . 4 2 9 ! . $ % 8 ) 4 % 8 ! - 0 , % ! & 4 % 2 ! 2 % ! $ # / - - ! . $ # , + # , + 4 4 4 4 4 4 4 4 n 4 n . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 n . / 0 2 e a d 2 e a d w ! 0 . / 0 . / 0 6 a l i d # o m m a n d $ 1 4 ! , . / 0 . / 0 # , 2 , 2 , " , ! c t i v e 0 o w e r $ o w n % n t r y # + % ! c t i v e 0 o w e r $ o w n % x i t # + t ) 3 t ) 3 ! # 4 ) 6 0 / 7 % 2 $ / 7 . - / $ % % . 4 2 9 ! . $ % 8 ) 4 % 8 ! - 0 , % ! & 4 % 2 ! 2 % ! $ # / - - ! . $ # , + # , + 4 4 4 4 4 4 4 4 n 4 n . / 0 . / 0 . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! # - $ $ 1 3 $ 1 3 4 n . / 0 2 e a d 2 e a d w ! 0 . / 0 . / 0 6 a l i d # o m m a n d $ 1 4 ! , . / 0 . / 0 # , 2 , 2 , " , ! c t i v e 0 o w e r $ o w n % n t r y # + % ! c t i v e 0 o w e r $ o w n % x i t t ) 3 t ) 3 t 8 ! 2 $ o r t 8 ! 2 $ 3 data sheet 55 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description figure 50 active power-down mode entry and exit example after a write command: wl = 4, t wtr =2,bl= 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. figure 51 active power-down mode entry and exit example after a write command with ap: wl = 4, wr = 3, bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mrs, address bit a12. wr is th e programmed value in the mrs mode register. ! # 4 ) 6 0 / 7 % 2 $ / 7 . - / $ % % . 4 2 9 ! . $ % 8 ) 4 % 8 ! - 0 , % ! & 4 % 2 ! 7 2 ) 4 % # / - - ! . $ # , + # , + 4 4 4 4 4 4 4 4 n 4 n . / 0 . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 4 n . / 0 7 r i t e . / 0 . / 0 6 a l i d # o m m a n d $ 1 4 . / 0 . / 0 7 , 2 , 7 , " , t 7 4 2 ! c t i v e 0 o w e r $ o w n % n t r y # + % ! c t i v e 0 o w e r $ o w n % x i t t ) 3 t ) 3 t 8 ! 2 $ o r t 8 ! 2 $ 3 t 7 4 2 . ! # 4 ) 6 0 / 7 % 2 $ / 7 . - / $ % % . 4 2 9 ! . $ % 8 ) 4 % 8 ! - 0 , % ! & 4 % 2 ! 7 2 ) 4 % # / - - ! . $ 7 ) 4 ( ! 0 # , + # , + 4 4 4 4 4 4 4 4 n 4 n . / 0 . / 0 $ i n ! $ i n ! $ i n ! $ i n ! # - $ $ 1 3 $ 1 3 4 n . / 0 7 r i t e w ! 0 . / 0 . / 0 6 a l i d # o m m a n d $ 1 4 . / 0 . / 0 7 , 2 , 7 , " , 7 2 ! c t i v e 0 o w e r $ o w n % n t r y # + % ! c t i v e 0 o w e r $ o w n % x i t t ) 3 t ) 3 t 8 ! 2 $ o r t 8 ! 2 $ 3 7 2 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 56 rev. 1.30, 2005-07 11222004-7n66-547b figure 52 precharge power down mode entry and exit note: ?pre-charge? may be an external command or an internal precharge following write with ap. figure 53 auto-refresh command to power-down entry figure 54 mrs, emrs command to power-down entry 0 2 % # ( ! 2 ' % 0 / 7 % 2 $ / 7 . - / $ % % . 4 2 9 ! . $ % 8 ) 4 # , + # , + 4 4 4 4 4 n 4 n 4 n # - $ t 8 0 0 r e c h a r g e . / 0 . / 0 . / 0 6 a l i d # o m m a n d t ) 3 t ) 3 . / 0 0 r e c h a r g e 0 o w e r $ o w n % n t r y 0 r e c h a r g e 0 o w e r $ o w n % x i t # + % . / 0 . / 0 4 ! 5 4 / 2 % & 2 % 3 ( # / - - ! . $ 4 / 0 / 7 % 2 $ / 7 . % . 4 2 9 # , + # , + 4 4 4 4 4 n # - $ t 8 0 ! u t o 2 e f r e s h 6 a l i d # o m m a n d t ) 3 t ) 3 # + % c a n g o l o w o n e c l o c k a f t e r a n ! u t o 2 e f r e s h c o m m a n d 7 h e n t 2 & # e x p i r e s t h e $ 2 ! - i s i n 0 r e c h a r g e 0 o w e r $ o w n - o d e # + % 4 t 2 & # - 2 3 % - 2 3 # / - - ! . $ 4 / 0 / 7 % 2 $ / 7 . % . 4 2 9 # , + # , + 4 4 4 4 4 # - $ - 2 3 o r % - 2 3 % n t e r s 0 r e c h a r g e 0 o w e r $ o w n - o d e # + % 4 t 2 & # 4 4 data sheet 57 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description 2.11 other commands 2.11.1 no operation command the no operation command (nop) should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registerin g any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a pr evious operation that is still executing, such as a burst read or write cycle. 2.11.2 deselect command the deselect command perfor ms the same function as a no operation command. de select command occurs when cs is brought high, the ras , cas , and we signals become don?t care. 2.12 dll-off mode clock speed operation range 2.13 input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: ? during self-refresh operation ? dram is in precharge power-down mode and odt is completely turned off. the ddr2-sdram has to be in precharged power- down mode and idle. odt must be already turned off and cke must be at a logic ?l ow? state. after a minimum of two clock cycles after t rp and t aofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a ?high? logic level again. after t xp has been satisfied a dll reset command via emrs(1) has to be issued. during the following dll re- lock period of 200 clock cycles, odt must remain off. after the dll-re-lock period the dram is ready to operate with the new clock frequency. figure 55 input frequency change example during precharge power-down mode table 16 dll-off mode clock speed operation range parameter product name min max unit clock frequency range for dll-off mode HYB18T256161AFL25 66 250 mhz hyb18t256161afl28 66 250 mhz hyb18t256161afl33 66 250 mhz # , + # , + 4 4 4 4 4 x 4 x 4 y 4 y 4 y . / 0 . / 0 # - $ 4 y . / 0 . / 0 . / 0 $ , , 2 % 3 % 4 4 . / 0 . / 0 & r e q u e n c y # h a n g e o c c u r s h e r e # + % . / 0 3 t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t 6 a l i d # o m m a n d 4 z t 2 0 t ! / & $ - i n i m u m c l o c k s r e q u i r e d b e f o r e c h a n g i n g t h e f r e q u e n c y t 8 0 c l o c k s / $ 4 i s o f f d u r i n g $ , , 2 % 3 % 4 hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram functional description data sheet 58 rev. 1.30, 2005-07 11222004-7n66-547b 2.14 asynchronous ck e low reset event in a given system, asynchronous reset event can occur at any time without prior knowledge. in this situation, memory controller is forced to drop cke asynchronously low, immediately interrupting any valid operation. dram requires cke to be maintained ?high? for all valid operations as defined in this data sheet. if cke asynchronously drop s ?low? during any valid operation, the dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. the dram must be fully re-initialized as described the initialization sequence (section 2.2.1, step 4 thru 13). dram is ready for normal operation after the initialization sequence. see chapter 7 . figure 56 asynchronous low reset event ! 3 9 . # ( 2 / . / 5 3 , / 7 2 % 3 % 4 % 6 % . 4 # , + # , + # + % d r o p s l o w d u e t o a n a s y n c h r o n o u s r e s e t e v e n t # + % # l o c k s c a n b e t u r n e d o f f a f t e r t h i s p o i n t t d e l a y 3 t a b l e c l o c k s data sheet 59 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram truth tables 3 truth tables table 17 command truth table function cke cs ras cas we ba0 ba1 ba2 a[12:11] a10 a[9:0] notes 1)2)3)4) 1) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 2) the state of odt does not affect the stat es described in this table. the odt functi on is not available during self refresh. 3) ?x? means ?h or l (but a defined logic level)?. 4) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 5) 5) bank addresses (bax) determine which bank is to be operated upon. for (e)mrs bax selects an (extended) mode register. auto-refresh h h l l l h x x x x self-refresh entry h l l l l h x x x x 6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 5) precharge all banks h h l l h l x x h x bank activate h h l l h h ba row address 5) write h h l h l l ba column l column 5)8) 8) burst reads or writes at bl = 4 cannot be terminated. see chapter 2.6.6 for details. write with auto- precharge h h l h l l ba column h column 5)8) read h h l h l h ba column l column 5)8) read with auto- precharge h h l h l h ba column h column 5)8) no operation h x l h h h x x x x device deselect h x h x x x x x x x power down entry h l h x x x x x x x 9) 9) the power down mode does not perform any refresh operations . the duration of power down is therefore limited by the refresh requirements outlined in chapter 2.9 . lh h h power down exit l h h x x x x x x x 4)9) lh h h hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram truth tables data sheet 60 rev. 1.30, 2005-07 11222004-7n66-547b table 18 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2) 3) ras , cas , we , cs 2) command (n) is the command registered at clock edge n, and action (n) is a result of command (n) 3) the state of odt does not affect the stat es described in this table. the odt func tion is not available during self refresh. action (n) 2) notes 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; cke (n-1) was the stat e of cke at the previous clock edge. current cycle 6) (n) power-down l l x mai ntain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refresh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 9)10)11)7) 9) all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) valid commands for po wer-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be regist ered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid leve l during the time period of t is + 2 t cke + t ih . self refresh l l x main tain self refresh 11)8)12) 12) v ref must be maintained during self refreh operation l h deselect or nop self refresh exit 9)13)14)12) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refr esh exit are nop and deselct only. bank(s) active h l deselect or nop activ e power-down entry 9)10)15)11)7) 15) power-down and self refresh can not be entered while re ad or write operations, (extende d) mode register operations, precharge or refresh operations are in progress. see chapter 2.10 and chapter 2.9.2 for a detailed list of restrictions. all banks idle h l deselect or nop precharge power-down entry 9)10)15)11) h l autorefresh self refresh entry 16)14)11)7) 16) self refresh mode can only be enter ed from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. table 19 data mask (dm) truth table name (function) dm dqs notes write enable l valid 1) 1) used to mask write data; provided co incident with the corresponding data. write inhibit h x 1) data sheet 61 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram absolute maximum ratings 4 absolute maximum ratings table 20 absolute maximum ratings symbol parameter rating units notes v dd voltage on v dd pin relative to v ss -1.0 to +2.3 v 1) 1) stresses greater than those listed under ?absolute maximum ratings? may ca use permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. v ddq voltage on v ddq pin relative to v ss -0.5 to +2.3 v 1) v ddl voltage on v ddl pin relative to v ss -0.5 to +2.3 v 1) v in , v out voltage on any pin relative to v ss -0.5 to +2.3 v 1) t stg storage temperature -55 to +150 c 1)2) 2) storage temperature is the case surface tem perature on the center/top side of the dram. t j junction temperature +125 c 1) hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics data sheet 62 rev. 1.30, 2005-07 11222004-7n66-547b 5 electrical characteristics 5.1 dc characteristics table 21 dram component operating temperature range symbol parameter rating units notes t oper operating temperature 0 to 85 o c 1)2)3) 1) operating temperature is the case surface temperature on the center / to p side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2) the operating temperature covers the temperature range where the full dram specification is supported. 3) above 85 o c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. table 22 rating for hyb18t256161af-22/-25/-28/-33 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.9 2.0 2.1 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v ddl supply voltage for dll 1.9 2.0 2.1 v 1) v ddq supply voltage for output 1.9 2.0 2.1 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination re sistors, is expect ed to be set equal to v ref , and must track variations in die dc level of v ref . table 23 rating for HYB18T256161AFL25/l28/l33 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v ddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination re sistors, is expect ed to be set equal to v ref , and must track variations in die dc level of v ref . data sheet 63 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics 5.2 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or fa lling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and char acterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. table 24 odt dc electrical characteristics parameter / condit ion symbol min. nom. max. units notes termination resistor impedance value for emrs(1)[a6,a2]= [0,1]; 75 ? rtt1 (eff) 60 75 95 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i ( v ihac ) and i ( v ilac ) respectively. rtt(eff) = ( v ih(ac) ? v il(ac) ) /( i ( v ihac ) ? i ( v ilac )). termination resistor impedance value for emrs(1)[a6,a2]=[1,0]; 150 ? rtt2 (eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)[a6,a2]=[1,1]; 50 ? rtt3 (eff) 40 50 65 ? 1) deviation of v m with respect to v ddq / 2 delta vm ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage ( v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m / v ddq ) ? 1) x 100%. table 25 input and output leakage currents symbol parameter / condit ion min. max. units notes i il input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v. i ol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off. table 26 dc & ac logic input levels symbol parameter min. max. units v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.250 v table 27 single-ended ac input test conditions symbol condition value units notes v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing(max) input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac)min to v ref for rising edges and the range from v ref to v il(ac)max for falling edges as shown in figure 57 . hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics data sheet 64 rev. 1.30, 2005-07 11222004-7n66-547b figure 57 single-ended ac input test conditions diagram figure 58 differential dc and ac input and output logic levels diagram 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac on the negative transitions. table 28 differential dc and ac input and output logic levels symbol parameter min. max. units notes v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac ) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which di fferential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which di fferential input signals must cross. v ddq v ih (ac) .min v ih (dc) .min v ref v il (dc) .max v il (ac) .max v ss v swing.max delta tr delta tf start of falling edge input timing start of rising edge input timing v ref - v il (ac).max delta tf falling slew = rising slew = v ih(ac).min - delta tr ref v crossing point vddq vssq vid vix or vox vtr vcp sstl18_3 data sheet 65 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics 5.3 output buffer characteristics table 29 sstl_18 output dc current drive symbol parameter sstl_18 unit note i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 2.0v +/- 0.1v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in 1) and 3) . they are used to test drive current capability to ensure v ih.min . plus a noise margin and v il.max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 2)3) 3) v ddq = 2.0v +/- 0.1v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. table 30 sstl_18 output ac test conditions symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and v ol is different from the referenced load described in chapter 8.1 . the sstl_18 test load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectiv ely 25 ohm termination resistor (13.4 ma 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates in to a minimum requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v 1) v otr output timing measurement reference level 0.5 v ddq v table 31 ocd default characteristics symbol description min. nominal max. unit note ? output impedance 12.6 18 23.4 ohms 1)2) 1) v ddq = 2.0v +/- 0.1v; v dd = 2.0v +/- 0.1v 2) impedance measurement condition for output source dc current: v ddq = 2.0v +/- 0.1v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement condition for output sink dc current: v ddq = 2.0v +/- 0.1v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 ohms 1)2)3) 3) mismatch is absolute value between pull-up and pull- down, both measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 ohms 4) 4) this represents the step size when the ocd is near 18 ohms at nominal conditions across all process parameters and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 1)5)6)7)8) 5) slew rates according to chapter 8.2.1 v il(ac) to v ih(ac) with the load specified in figure 63 . 6) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is verified by design and characterization but not su bject to production test. 7) timing skew due to dram output sl ew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification. 8) dram output slew rate specification applies to 400 and 533 mt/s speed bins. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics data sheet 66 rev. 1.30, 2005-07 11222004-7n66-547b 5.4 default output v-i characteristics ddr2 sdram output driver characteristics are defined for full strength default operation as selected by the emrs(1) bits a[9:7] =?111?. figure 59 and figure 60 show the driver characteri stics graphically and the tables show the same data suitable for input into simulation tools. note: the driver characteristic s evaluation conditions are: 1. nominal default 25 o c (tcase), v ddq = 2.0 v, typical process 2. minimum: t case = 85 o c, v ddq = 1.9 v, slow?slow process 3. maximum: t case = 0 o c, v ddq = 2.1 v, fast?fast process table 32 full strength default pu ll-up driver characteristics voltage (v) pull-up driver current [ma] min. nominal default low nominal default high max. 0.2 ?8.5 ?11.1 ?11.8 ?15.9 0.3 ?12.1 ?16.0 ?17.0 ?23.8 0.4 ?14.7 ?20.3 ?22.2 ?31.8 0.5 ?16.4 ?24.0 ?27.5 ?39.7 0.6 ?17.8 ?27.2 ?32.4 ?47.7 0.7 ?18.6 ?29.8 ?36.9 ?55.0 0.8 ?19.0 ?31.9 ?40.8 ?62.3 0.9 ?19.3 ?33.4 ?44.5 ?69.4 1.0 ?19.7 ?34.6 ?47.7 ?75.3 1.1 ?19.9 ?35.5 ?50.4 ?80.5 1.2 ?20.0 ?36.2 ?52.5 ?84.6 1.3 ?20.1 ?36.8 ?54.2 ?87.7 1.4 ?20.2 ?37.2 ?55.9 ?90.8 1.5 ?20.3 ?37.7 ?57.1 ?92.9 1.6 ?20.4 ?38.0 ?58.4 ?94.9 1.7 ?20.6 ?38.4 ?59.6 ?97.0 1.8 ? ?38.6 ?60.8 ?99.1 1.9 ? ? ? ?101.1 data sheet 67 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics figure 59 full strength default pull-up driver diagram note: the driver characteristic s evaluation conditions are: 1. nominal default 25 o c ( t case ), v ddq = 2.0 v, typical process, 2. minimum: t case = 85 o c, v ddq = 1.9 v, slow?slow process 3. maximum: t case = 0 o c, v ddq = 2.1 v, fast?fast process table 33 full strength default pull?down driver characteristics voltage (v) pull-down driver current [ma] minimum nominal default low n ominal default high maximum 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 ? 37.9 60.9 99.1 1.9 ? ? ? 101.1 -120 -100 -80 -60 -40 -20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vddq to vout (v) pullup current (ma) minimum nominal default low nominal default high maximum hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics data sheet 68 rev. 1.30, 2005-07 11222004-7n66-547b figure 60 full strength default pull?down driver diagram 5.4.1 calibrated output dr iver v-i characteristics ddr2 sdram output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the off-chip driver (ocd) impedance adjustment. the table 34 and table 35 show the data in tabular format suitable for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves are represented here or in supplier ibis models need to be adjusted to a wider range as a result of any system calibration error. since this is a system specif ic phenomena, it cannot be quantified here. the values in the calibrated tables represent just the dram po rtion of uncertainty while looking at one dq only. if the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the defa ult device characteristics tables and figure. in such a situation, the timing parameters in the specification cannot be guaranteed. it is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at a ll times. if this can?t be guaranteed by the system calibration procedure, re- calibration policy and uncertainty with dq to dq variation, it is recommended that only the default values to be used. the nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. 0 20 40 60 80 100 120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vout to vssq (v) pulldown current (ma) minimum nominal default low nominal default high maximum data sheet 69 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics note: the driver characteristic s evaluation conditions are: 1. nominal 25 o c ( t case ), v ddq = 2.0 v, typical process 2. nominal low and nominal high: t case = 25 o c , v ddq = 2.0 v, any process 3. nominal minimum: t case = 85 o c, v ddq = 1.9 v, any process 4. nominal maximum: t case = 0 o c, v ddq = 2.1 v, any process note: the driver characteristic s evaluation conditions are: 1. nominal 25 o c ( t case ), v ddq = 2.0 v, typical process 2. nominal low and nominal high 25 o c ( t case ), v ddq = 2.0 v, any process 3. nominal minimum: t case = 85 o c, v ddq = 1.9 v, any process 4. nominal maximum: t case = 0 o c, v ddq = 2.1 v, any process 5.5 input / output capacitance table 34 full strength calibrated pu ll-down driver characteristics voltage (v) calibrated pull-down driver current [ma] nominal minimum (21 ohms) normal low (18.75 ohms) nominal (18 ohms) normal high (17.25 ohms) nominal maximum (15 ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 table 35 full strength calibrated pull-up driv er characteristics voltage (v) calibrated pull-up driver current [ma] nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.25 ohms) nominal maximum (15 ohms) 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 table 36 input / output capacitance symbol parameter min. max. units cck input capacitance, ck and ck 0.5 1.5 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 0.5 1.5 pf cdi input capacitance delta, a ll other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?0.25 pf hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics data sheet 70 rev. 1.30, 2005-07 11222004-7n66-547b 5.6 power & ground clam p v-i characteristics power and ground clamps are provided on address (a[13:0], ba[2:0]), ras , cas , cs , we , cke and odt pins. the v-i characteristics for pins with clamps is shown in table 37 . table 37 power & ground clamp v-i characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 data sheet 71 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics 5.7 overshoot and unde rshoot specification figure 61 ac overshoot / undershoot diagram for address and control pins figure 62 ac overshoot / undershoot diagram for clock, data, strobe and mask pins table 38 ac overshoot / undershoot specification for address and control pins parameter ddr2?900 ddr2?800 ddr2?700 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v dd 0.75 0.75 0.75 v.ns maximum undershoot area below v ss 0.75 0.75 0.75 v.ns table 39 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2?900 ddr2?800 ddr2?700 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.38 0.38 v.ns maximum undershoot area below v ssq 0.38 0.38 0.38 v.ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram i dd specifications and conditions data sheet 72 rev. 1.30, 2005-07 11222004-7n66-547b 6 i dd specifications and conditions table 40 i dd measurement conditions parameter symbol notes 1)2)3)4)5)6) operating current 0 one bank active - precharge; t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , cke is high, cs is high between valid commands. address and co ntrol inputs are switch ing, databus inputs are switching . i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , t rcd = t rcdmin. ,al = 0, cl = cl min .; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge power-down current all banks idle; cke is low; t ck = t ckmin ; other control and address inputs are stable, data bus inputs are floating . i dd2p precharge standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are switching, data bus in puts are switching. i dd2n precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are stable, data bus in puts are floating. i dd2q active power-down current all banks open; t ck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin .; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ckmin ., refresh command every t rfc = t rfcmin. interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ckmin. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d data sheet 73 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram i dd specifications and conditions self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs ar e floating. reset = low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current 3. all banks interleaving reads, i out = 0 ma; bl = 4, cl=cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; t faw = t faw(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. i dd7 1) v ddq = 2.0v +/- 0.1v; v dd = 2.0v +/- 0.1v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : low is defined as v in v il(ac)max ; high is defined as v in v ih(ac)min ; stable is defined as inputs are stable at a high or lo w level; floating is defined as inputs are v ref = v ddq / 2; switching is defined as: inputs are changing between high and low every other clock (once pe r two clocks) for address and control signals, and inputs changing between high and low every other clock (once pe r clock) for dq signals not including mask or strobes. 6) timing parameter minimum and maximum values for i dd current measurements are defined in table 42 . table 41 i dd specification product type speed code ?2.2 ?2.5 ?2.8 ?3.3 unit notes speed grade ddr2 ? 900 ddr2 ? 800 ddr2 ? 700 ddr2 ? 600 symbol typ. typ. typ. typ. i dd0 90 80 70 60 ma i dd1 95 85 70 65 ma i dd2p 4444ma i dd2n 45 40 35 30 ma i dd2q 40 35 30 25 ma i dd3p 20 20 15 15 ma 4444ma i dd3n 50 45 40 35 ma i dd4r 140 130 120 115 ma i dd4w 180 170 160 155 ma i dd5b 130 120 110 110 ma i dd5d 5555ma i dd6 8888ma i dd7 190 180 170 160 ma table 40 i dd measurement conditions parameter symbol notes 1)2)3)4)5)6) hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram i dd specifications and conditions data sheet 74 rev. 1.30, 2005-07 11222004-7n66-547b 6.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: 6.2 on die termination (odt) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?week? or ?strong? termination can be selected. the current consumption for any terminated input pin depends on weather the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time. see table 43 . note: for power consumption calculations the od t duty cycle has to be taken into account. table 42 idd measurement test condition parameter symbol -2.2 -2 .5 -2.8 -3.3 units notes ddr2? 900 ddr2? 800 ddr2? 700 ddr2? 600 cas latency cl min cl= 6 450 400 350 300 t ck cl= 5 400 400 350 300 clock cycle time t ckmin cl= 6 2.2 2.5 2.86 3.3 ns cl= 5 2.5 2.5 2.86 3.3 active to read or write delay t rcdmi n 15 15 15 15 ns active to active / auto-refresh command period t rcmin 60 60 60 60 ns active bank a to active bank b command delay t rrdmi n 7.5 7.5 7.5 7.5 ns active to precharge command t rasmi n 45 45 45 45 ns precharge command period t rpmin 15 15 15 15 ns auto-refresh to acti ve / auto-refresh command period t rfcmi n 75 75 75 75 ns table 43 odt current per terminated input pin: odt current emrs(1) state min. typ. max. unit enabled odt current per dq added i ddq current for odt enabled; odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq active odt current per dq added i ddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq data sheet 75 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification 7 electrical characteristics & ac timing - absolute specification table 44 timing parameters for hyb18t256161af-22/-25 1) symbol parameter ?2.2 ddr2?900 ?2.5 ddr2?800 unit notes min. max. min. max. f ck clock frequency cl=5 125 400 125 400 mhz cl=6 125 450 125 400 mhz t ac dq output access time from ck / ck ?0.45 0.45 ?0.50 0.50 ns t dqsck dqs output access time from ck / ck ?0.45 0.45 ?.500 .500 ns t ch ck, ck high-level width 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 t ck t hp clock half period min ( t cl , t hp) ?min ( t cl , t hp) ? t ck t is address and control input setup time 0.65 ? 0.70 ? ns 2) t ih address and control input hold time 0.65 ? 0.70 ? ns 2) t ds dq and dm input setup time 0.345 ? 0.375 ? ns 2) t dh dq and dm input hold time 0.345 ? 0.375 ? ns 2) t ipw address and control input pulse width (each input) 0.60 ? 0.60 ? t ck t dipw dq and dm input pulse width (each input) 0.35 ? 0.35 ? t ck t hz data-out high-impedance time from ck / ck ? t acmax ? t acmax ps t lz(dq) dq low-impedance time from ck / ck 2 t acmin t acmax 2 t acmin t acmax ps t lz(dqs) dqs low-impedance from ck / ck t acmin t acmax t acmin t acmax ps t dqsq dqs-dq skew (for dqs & associated dq signals) ? 320 ? 350 ps t qhs data hold skew factor ? 320 ? 350 ps t qh data output hold time from dqs t hp ? t qhs ? t hp ? t qhs ? t dqss write command to 1st dqs latching transition wl ? 0.25 wl +0.25 wl ? 0.25 wl +0.25 t ck t dqsh dqs input low (high) pulse wi dth (write cycle) 0.35 ? 0.35 ? t ck t dqsl dqs input low (high) pulse wi dth (write cycle) 0.35 ? 0.35 ? t ck t dss dqs falling edge to ck setup time (write cycle) 0.20 ? 0.20 ? t ck t dsh dqs falling edge hold ti me from ck (write cycle) 0.20 ? 0.20 ? t ck t mrd mode register set command cycle time 2 ? 2 ? t ck t wpre write preamble 0.25 ? 0.25 ? t ck t wpst write postamble 0.40 0.60 0.40 0.60 t ck t rpre read preamble 0.90 1.10 0.90 1.10 t ck t rpst read postamble 0.60 0.40 0.60 t ck t ras active to precharge command 45 70000 45 70000 ns t rc active to active/auto-refresh command period 60 ? 60 ? ns t rfc auto-refresh to active/auto-refresh command period 75 ? 75 ? ns hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification data sheet 76 rev. 1.30, 2005-07 11222004-7n66-547b t rcd active to read or write delay (with and without auto-precharge) ??15?ns t rp precharge command period 16 ? 15 ? ns t rrd active bank a to active bank b command period 9?7.5?ns t ccd cas a to cas b command period 2 ? 2 ? t ck t wr write recovery time 14 ? 15 ? ns t dal auto-precharge write recovery + precharge time wr + t rp ?wr + t rp ? t ck t wtr internal write to read command delay 7.5 ? 7.5 ? ns t rtp internal read to precharge command delay 7.5 ? 7.5 ? ns t xard exit power down to any valid command (other than nop or deselect) 2?2? t ck t xards exit active power-down mode to read command (slow exit, lower power) 6 - al ? 6 - al ? t ck t xp exit precharge power-down to any valid command (other than nop or deselect) 2?2? t ck t xsrd exit self-refresh to read command 200 ? 200 ? t ck t xsnr exit self-refresh to non-read command t rfc + 10 ? t rfc + 10 ? ns t cke cke minimum high and low pulse width 3 ? 3 ? t ck t refi average periodic refresh interval ? 7.8 ? 7.8 s 3) 4) ? 3.9 ? 3.9 s t oit ocd drive mode output delay 0 12 0 12 ns t delay minimum time clocks remain on after cke asynchronously drops low t is + t ck + t i h ?? t is + t ck + t i h ?ns 1) all parameters are based on v dd 2.0 v 0.1 v 2) timing is based on signal to v ref -crossing 3) 0c - 85c 4) 85c and above table 45 timing parameters for hyb18t256161af-28/-33 1) symbol parameter ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. f ck clock frequency cl=5 125 350 125 300 mhz cl=6 125 350 125 300 mhz t ac dq output access time from ck / ck ?0.55 0.55 ?0.60 0.60 ns t dqsck dqs output access time from ck / ck ?.550 .550 ?.600 .600 ns t ch ck, ck high-level width 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 t ck table 44 timing parameters for hyb18t256161af-22/-25 1) symbol parameter ?2.2 ddr2?900 ?2.5 ddr2?800 unit notes min. max. min. max. data sheet 77 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification t hp clock half period min ( t cl , t hp) ? min ( t cl , t hp) ? t ck t is address and control input setup time 0.75 ? 0.80 ? ns 2) t ih address and control input hold time 0.75 ? 0.80 ? ns 2) t ds dq and dm input setup time 0.400 ? 0.425 ? ns 2) t dh dq and dm input hold time 0.400 ? 0.425 ? ns 2) t ipw address and control input pulse width (each input) 0.60 ? 0.60 ? t ck t dipw dq and dm input pulse width (each input) 0.35 ? 0.35 ? t ck t hz data-out high-impedance time from ck / ck ? t acmax ? t acmax ps t lz(dq) dq low-impedance time from ck / ck 2 t acmin t acmax 2 t acmin t acmax ps t lz(dqs) dqs low-impedance from ck / ck t acmin t acmax t acmin t acmax ps t dqsq dqs-dq skew (for dqs & associated dq signals) ?350 ?350 ps t qhs data hold skew factor ? 350 ?350 ps t qh data output hold time from dqs t hp ? t qhs ? t hp ? t qhs ? t dqss write command to 1st dqs latching transition wl ? 0.25 wl +0.25 wl ? 0.25 wl +0.25 t ck t dqsh dqs input low (high) puls e width (write cycle) 0.35 ? 0.35 ? t ck t dqsl dqs input low (high) puls e width (write cycle) 0.35 ? 0.35 ? t ck t dss dqs falling edge to ck setu p time (write cycle) 0.20 ? 0.20 ? t ck t dsh dqs falling edge hold ti me from ck (write cycle) 0.20 ? 0.20 ? t ck t mrd mode register set command cycle time 2 ? 2? t ck t wpre write preamble 0.25 ? 0.25 ? t ck t wpst write postamble 0.40 0.60 0.40 0.60 t ck t rpre read preamble 0.90 1.10 0.90 1.10 t ck t rpst read postamble 0.40 0.60 0.40 0.60 t ck t ras active to precharge command 45 70000 45 70000 ns t rc active to active/auto-refresh command period 60 ? 60 ? ns t rfc auto-refresh to active/auto-refresh command period 75 ? 75 ? ns t rcd active to read or write delay (with and without auto-precharge) 15 ? 15 ? ns t rp precharge command period 15 ? 15 ? ns t rrd active bank a to active bank b command period 7.5 ? 7.5 ? ns t ccd cas a to cas b command period 2 ? 2? t ck t wr write recovery time 15 ? 15 ? ns table 45 timing parameters for hyb18t256161af-28/-33 1) symbol parameter ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification data sheet 78 rev. 1.30, 2005-07 11222004-7n66-547b t dal auto-precharge write recovery + precharge time wr + t rp ? wr + t rp ? t ck t wtr internal write to read command delay 7.5 ? 7.5 ? ns t rtp internal read to prec harge command delay 7.5 ? 7.5 ? ns t xard exit power down to any valid command (other than nop or deselect) 2? 2? t ck t xards exit active power-down mode to read command (slow exit, lower power) 6 - al ? 6 - al ? t ck t xp exit precharge power-down to any valid command (other than nop or deselect) 2? 2? t ck t xsrd exit self-refresh to read command 200 ? 200 ? t ck t xsnr exit self-refresh to non-read command t rfc + 10 ? t rfc + 10 ? ns t cke cke minimum high and low pulse width 3 ? 3? t ck t refi average periodic refresh interval ? 7.8 ?7.8 s 3) 4) ?3.9 ?3.9 s t oit ocd drive mode output delay 0 12 012 ns t delay minimum time clocks remain on after cke asynchronously drops low t is + t ck + t i h ? t is + t ck + t i h ?? ns 1) all parameters are based on v dd 2.0 v 0.1 v 2) timing is based on signal to v ref -crossing 3) 0c - 85c 4) 85c and above table 46 timing parameters for HYB18T256161AFL25/l28/l33 1) symbol parameter ?2.5 ddr2?800 ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. min. max. f ck clock frequency cl=5 125 400 125 350 125 300 mhz cl=6 125 400 125 350 125 300 mhz t ac dq output access time from ck / ck ?0.50 0.50 ?0.55 0.55 ?0.60 0.60 ns t dqsck dqs output access time from ck / ck ?.500 .500 ?.550 .550 ?.600 .600 ns t ch ck, ck high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck t hp clock half period min ( t cl , t hp) ?min ( t cl , t hp) ?min ( t cl , t hp) ? t ck t is address and control input setup time 0.70 ? 0.75 ? 0.80 ? ns 2) t ih address and control input hold time 0.70 ? 0.75 ? 0.80 ? ns 2) t ds dq and dm input setup time 0.375 ? 0.400 ? 0.425 ? ns 2) table 45 timing parameters for hyb18t256161af-28/-33 1) symbol parameter ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. data sheet 79 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification t dh dq and dm input hold time 0.375 ? 0.400 ? 0.425 ? ns 2) t ipw address and control input pulse width (each input) 0.60 ? 0.60 ? 0.60 ? t ck t dipw dq and dm input pulse width (each input) 0.35 ? 0.35 ? 0.35 ? t ck t hz data-out high-impedance time from ck / ck ? t acma x ? t acma x ? t acma x ps t lz(dq) dq low-impedance time from ck / ck 2 t acmi n t acma x 2 t acmi n t acma x 2 t acmi n t acma x ps t lz(dqs) dqs low-impedance from ck / ck t acmin t acma x t acmin t acma x t acmin t acma x ps t dqsq dqs-dq skew (for dqs & associated dq signals) ?350?350?350ps t qhs data hold skew factor ? 350 ? 350 ? 350 ps t qh data output hold time from dqs t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? t dqss write command to 1st dqs latching transition wl ? 0.25 wl +0.2 5 wl ? 0.25 wl +0.2 5 wl ? 0.25 wl +0.2 5 t ck t dqsh dqs input low (hig h) pulse width (write cycle) 0.35 ? 0.35 ? 0.35 ? t ck t dqsl dqs input low (hig h) pulse width (write cycle) 0.35 ? 0.35 ? 0.35 ? t ck t dss dqs falling edge to ck setup time (write cycle) 0.20 ? 0.20 ? 0.20 ? t ck t dsh dqs falling edge hold time from ck (write cycle) 0.20 ? 0.20 ? 0.20 ? t ck t mrd mode register set command cycle time 2?2?2? t ck t wpre write preamble 0.25 ? 0.25 ? 0.25 ? t ck t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck t rpre read preamble 0.90 1.10 0.90 1.10 0.90 1.10 t ck t rpst read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck t ras active to precharge command 45 7000 0 45 7000 0 45 7000 0 ns t rc active to active/auto-refresh command period 60 ? 60 ? 60 ? ns t rfc auto-refresh to active/auto-refresh command period 75 ? 75 ? 75 ? ns t rcd active to read or write delay (with and without auto-precharge) 15 ? 15 ? 15 ? ns t rp precharge command period 15 ? 15 ? 15 ? ns table 46 timing parameters for HYB18T256161AFL25/l28/l33 1) symbol parameter ?2.5 ddr2?800 ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. min. max. hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram electrical characteristics & ac timing - absolute specification data sheet 80 rev. 1.30, 2005-07 11222004-7n66-547b t rrd active bank a to active bank b command period 7.5?7.5?7.5?ns t ccd cas a to cas b command period2?2?2? t ck t wr write recovery time 15 ? 15 ? 15 ? ns t dal auto-precharge write recovery + precharge time wr + t rp ?wr + t rp ?wr + t rp ? t ck t wtr internal write to read command delay 7.5?7.5?7.5?ns t rtp internal read to precharge command delay 7.5?7.5?7.5?ns t xard exit power down to any valid command (other than nop or deselect) 2?2?2? t ck t xards exit active power-down mode to read command (slow exit, lower power) 6 - al ? 6 - al ? 6 - al ? t ck t xp exit precharge power-down to any valid command (other than nop or deselect) 2?2?2? t ck t xsrd exit self-refresh to read command 200 ? 200 ? 200 ? t ck t xsnr exit self-refresh to non-read command t rfc + 10 ? t rfc + 10 ? t rfc + 10 ?ns t cke cke minimum high and low pulse width 3?3?3? t ck t refi average periodic refresh interval ? 7.8 ? 7.8 ? 7.8 s 3) 4) ?3.9?3.9?3.9 s t oit ocd drive mode output delay 0 12 0 12 0 12 ns t delay minimum time clocks remain on after cke asynchronously drops low t is + t ck + t ih ? t is + t ck + t ih ? t is + t ck + t ih ?? ns 1) all parameters are based on v dd 1.8 v 0.1 v 2) timing is based on signal to v ref -crossing 3) 0c - 85c 4) 85c and above table 46 timing parameters for HYB18T256161AFL25/l28/l33 1) symbol parameter ?2.5 ddr2?800 ?2.8 ddr2?700 ?3.3 ddr2?600 unit notes min. max. min. max. min. max. data sheet 81 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions 8 ac timing measurement conditions 8.1 reference load for timing measurements figure 63 represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing re ference load to a system environment. manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. this reference load is also used for output slew rate characterization. the output timing reference voltage level for single ended signals is the crosspoint with v tt . the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. figure 63 reference load for timing measurements 8.2 slew rate measurement conditions 8.2.1 output slewrate with the reference load for timing measurements output slew rate for falling and rising edges is measured between v tt ? 250 mv and v tt + 250 mv for single ended signals. for differential signals ( dqs / dqs ) output slew rate is measured between dqs - dqs = 500 mv and dqs ? dqs = ?500 mv. output slew rate is defined with the reference load according to figure 63 and verified by design and characterization, but not subject to production testt. 8.2.2 input slewrate - differential signals input slewrate for differential signals (ck / ck , dqs / dqs , rdqs / rdqs ) for rising edges are measured from ck - ck = ?250 mv to ck ? ck = +500 mv and from ck ? ck = +250 mv to ck ? ck = ?500mv for falling edges. 8.2.3 input slewrate - single ended signals input slew rate for single ended signals (other than t is , t ih , t ds and t dh ) are measured from dc-level to ac-level: v ref ?125 mv to v ref + 250 mv for rising edges and from v ref + 125 mv to v ref ? 250 mv for falling edges. for slew rate definition of the input and data setup and hold parameters see chapter 8.3 of this data sheet. 25 ohm v tt = v ddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions data sheet 82 rev. 1.30, 2005-07 11222004-7n66-547b 8.3 input and data setup and hold time 8.3.1 timing definition for input setup ( t is ) and hold time ( t ih ) address and control input setup time ( t is ) is referenced from the input signal crossing at the v ih(ac) level for a rising signal and v il(ac) for a falling signal applied to the device under test. address and control input hold time ( t ih ) is referenced from the input signal crossing at the v il(dc) level for a rising signal and v ih(dc) for a falling signal applied to the device under test. figure 64 timing definition for input setup (tis) and hold time (tih) 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes data input setup time ( t ds ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs/dqs signals must be monotonic between v il(dc).max and v ih(dc).min . data input hold time ( t dh ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v il(dc) level to the differential data strobe crosspoint for a rising signal and v ih(dc) to the differential data strobe crosspoint for a falling sign al applied to the device under test. dqs/dqs signals must be monotonic between v il(dc).max and v ih(dc.min . data sheet 83 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions figure 65 data, setup and hold time diagram (differential data strobes) 8.3.3 definition for data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes data input se tup time ( t ds1 ) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(ac) level to the single- ended data strobe crossing v ih/l(dc) at the start of its transition for a rising signal, and from the input signal crossing at the v il(ac) level to the single-ended data strobe crossing v ih/l(dc) at the start of its transition for a falling signal applied to the device under test. data input hold time ( tdh1 ) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(dc) level to the single- ended data strobe crossing v ih/l(ac) at the end of its transition for a rising signal and from the input signal crossing at the v il(dc) level to the single-ended data strobe crossing v ih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between v il(dc.max and v ih(dc).min . v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t ds t dh t ds t dh dqs dqs hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions data sheet 84 rev. 1.30, 2005-07 11222004-7n66-547b figure 66 data setup and hold time (single ended data strobes) t ds t dh t ds t dh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss dqs dq data sheet 85 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions 8.3.4 slew rate definition for input and data setup and hold times setup ( t is & t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac).min . setup ( t is & t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac).max . if the actual signal is always earlier than the nominal slew rate line between shaded ? v ref(dc) to ac region?, use nominal slew rate for derating value (see figure 67 ). if the actual signal is later than the nominal slew rate line anywhere between shaded ? v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(see figure 68 ) hold ( t ih & t dh ) nominal slew rate for a rising si gnal is defined as the slew rate between the last crossing of v il(dc).max and the first crossing of v ref(dc) . hold ( t ih & t dh ) nominal slew rate for a falling signal is defined as the slew rate between the la st crossing of v ih(dc).min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref region?, use nominal slew rate for derating value (see figure 67 ). if the actual signal is earlier than the actual signal from the dc level to v ref level is used for derating value (see figure 68 ) figure 67 slew rate definition nominal note: v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs dc to vref region vref to ac region dc to vref region vref to ac region ck, ck for tis and tih dqs, dqs for tds and td h t is t ds t ih t dh t is t ds t ih t dh setup slew rate = vref(dc) - vil(ac)max delta tfs falling signal setup slew rate = vih(ac)min - vref(dc) delta trs rising signal hold slew rate = vref(dc) - vil(dc)max delta trh rising signal hold slew rate = vih(dc)min - vref(dc) delta tfh falling signal hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions data sheet 86 rev. 1.30, 2005-07 11222004-7n66-547b figure 68 slew rate definition tangent note: v ss v il (ac) max v il (dc) max v ref v ih (dc) min v ddq v ih (ac) min vref to ac region vref to ac region tangent line tangent line nominal line nominal line delta tr delta tf ck,dqs ck,dqs t is ,t ds t ih ,t dh t is ,t ds t ih ,t dh setup slew rate = tangent line [vref(dc) - vil(ac)max] delta tfs setup slew rate = tangent line [vih(ac)min - vref(dc)] delta trs hold slew rate = tangent line [vref(dc) - vil(dc)max] delta trh hold slew rate = tangent line [vih(dc)min - vref(dc)] delta tfh falling signal falling signal rising signal rising signal data sheet 87 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables 1. for all input signals the total input setup time and input hold time required is calculated by adding the data sheet value to the derating value respectively. example: t is (total setup tine) = t is (base) + ? t is 2. for slow slew rate the total setup time might be negative (i.e. a valid in put signal will not have reached v ih(ac) / v il(ac) at the time of the rising clock) a valid input signal is st ill required to complete the transition and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. these val ues are not subject to production test. they are verified only by design and characterization. table 47 input setup ( t is ) and hold ( t ih ) time derating values command / address slew rate (v/ns) ck, ck differential slew rate unit note 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih 4.0 +187 +94 +217 +124 +247 +154 ps 1) 1) for all input signals t is (total) = t is (base) + ? t is and t ih (total) = t ih (base) + ? t ih 3.5 +179 +89 +209 +119 +239 +149 ps 1) 3.0 +167 +83 +197 +113 +227 +143 ps 1) 2.5 +150 +75 +180 +105 +210 +135 ps 1) 2.0 +125 +45 +155 +75 +185 +105 ps 1) 1.5 +83 +21 +113 +51 +143 +81 ps 1) 1.0 0 0 +30 +30 +60 +60 ps 1) 0.9 ?11 ?14 +19 +16 +49 +46 ps 1) 0.8 ?25 ?31 +5 ?1 +35 +29 ps 1) 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 1) 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 1) 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 1) 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 1) 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 1) 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 1) 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 1) 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 1) 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps 1) hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram ac timing measurement conditions data sheet 88 rev. 1.30, 2005-07 11222004-7n66-547b table 48 data setup ( t ds ) and hold time ( t dh ) derating values for differential dqs/dqs 1)2) 1) all units in ps. 2) for all input signals t ds (total) = t ds (base) + ? t ds and t dh (total) = t dh (base) + ? t dh dq slew rate (v/ns) dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0 +125+45+125+45+125+45??????? ????? 1.5 +83+21+83+21+83+21+95+33????? ????? 1.00 00 00 0+12+12+24+24???????? 0.9???11?14?11?14+1?2+13+10+25+22?????? 0.8 ? ? ? ? ?25 ?31 ?13 ?19 ?1 ?7 +11 +5 +23 +17 ? ? ? ? 0.7 ? ? ? ? ? ? ?31 ?42 ?19 ?30 ?7 ?18 +5 ?6 +17 +6 ? ? 0.6 ? ? ? ? ? ? ? ? ?43 ?49 ?31 ?47 ?19 ?35 ?7 ?23 +5 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?74 ?89 ?62 ?77 ?50 ?65 ?38 ?53 0.4 ? ?? ?? ????????127?140?115?128?103?116 table 49 data setup ( t ds ) and hold time ( t dh ) derating values for single ended dqs 1)2)3) 1) all units in ps. 2) for all input signals t ds1 (total) = t ds1 (base) + ? t ds1 and t dh1 (total) = t dh1 (base) + ? t dh1 3) for slow slew rate the total setup time might be negative (i.e. a valid input signal will not have reached v ih(ac) / v il(ac) at the time of the rising dqs) a valid input signal is still required to complete the transition and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the table, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterization. dq slew rate (v/ns) dqs single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns ? t d1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 2.0+125+45+125+45+125+45------------ 1.5+83+21+83+21+83+21+95+33---------- 1.00 00000+12+12+24+24-------- 0.9- --11-14-11-14+1-2+13+10+25+22------ 0.8- -- --25-31-13-19-1-7+11+5+23+17---- 0.7- -- -- --31-42-19-30-7-18+5-6+17+6- - 0.6- -- -- ----43-49-31-47-19-35-7-23+5-11 0.5- -- -- ------74-89-62-77-50-65-38-53 0.4- -- -- --------127-140-115-128-103-116 data sheet 89 rev. 1.30, 2005-07 11222004-7n66-547b hyb18t256161af?[22/25/ 28/33] l[25/28/33] 256-mbit ddr2 sgram package 9 package 9.1 package outline 9.2 package thermal characterist table 50 t-fbga-84 package thermal resistance odt current theta-ja 1) 1) theta-ja: junction to ambient thermal resistance. the values have been obtained by simulating using the conditions stated in the jedec jesd-51 standard. theta-jl 2) 2) theta_jl: junction to lead thermal resistance (not according jesd-51). the value has been obtained by simulation. theta-jc 3) 3) theta_jc: junction to case thermal resistance. the value has been obtained by simulation . jedec board 1 s0p 2s2p air flow 0m/s 1m/s 3m/s 0m/s 1m/s 3m/s ? ? r th k/w 69534741353318 5 12.5 11.2 14 x 0.8 = 1) a 4) 3) b 2) 0.05 ?0.46 ?0.08 m ?0.15 84x m c ab 1.2 max. 0.31 min. c seating plane 2) middle of packages edges 4) bad unit marking (bum) 3) package orientation mark a1 1) dummy pads without ball 2) 5) 5) die sort fiducial 0.8 0.2 0.8 8 x 0.8 = 6.4 10 0.18 max. c 0.1 0.1 c 2.2 max. published by infineon technologies ag www.infineon.com |
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